IP Library Granted Patent US 10,352,996
Granted Patent B2
US 10,352,996 · App. 15/350,902 · Granted Jul 16, 2019

Backplane testing system

Inventors: Umesh Chandra (Santa Cruz, CA); Timothy Thinh Mai (San Jose, CA)
Assignee: Dell Products L.P.
G01R31/31703G01R31/3177G01R31/31708G01R31/31712G01R31/31716G01R31/31813G01R31/31907G06F11/00
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Quick Facts
Patent No.
US 10,352,996
App. No.
15/350,902
Granted
Jul 16, 2019
Kind
B2
Abstract

A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.

Claims (49)

1. A backplane testing system, comprising:

a backplane that includes a first connector system, a second connector system, and a plurality of channels that connect the first connector system and the second connector system;

a first test device that engages the first connector system and that includes a loop back circuit;

a second test device that engages the second connector system and that is configured to:

send a test signal through the second connector system such that the test signal is provided through at least one of the plurality of channels on the backplane and through the first connector system to the loop back circuit on the first test device; and

receive the test signal back through second connector system in response to the loop back circuit routing the test signal through the first connector system such that the test signal is provided through at least one of the plurality of channels on the backplane and through the second connector system; and

at least one subsystem that is configured to:

analyze the test signal that was received by the second test device to determine a testing compliance of the at least one of the plurality of channels on the backplane.

2. The backplane testing system of claim 1 , wherein the backplane is a networking device backplane, the first connector system is a line module connector system, and the second connector system is a route processing module connector system.

3. The backplane testing system of claim 1 , wherein the first test device engages the first connector system that is configured to connect a plurality of devices to the backplane.

4. The backplane testing system of claim 1 , wherein the first test device engages a transmitter connection and a receiver connection on the first connector system to connect the transmitter connection and the receiver connection to the loop back circuit.

5. The backplane testing system of claim 1 , further comprising:

an analyzer system that is coupled to the second test device and that is configured to:

create the test signal that includes a pseudorandom binary sequence (PRBS) test pattern; and

analyze a received PRBS test pattern in the test signal that is received by the second test device to determine the testing compliance of the at least one of the plurality of channels on the backplane.

6. The backplane testing system of claim 1 , further comprising:

a testing system that is coupled to the second test device, wherein the testing system is configured to:

determine eye details of the test signal that is received by the second test device.

7. The backplane testing system of claim 1 , wherein the testing compliance of the at least one of the plurality of channels on the backplane is a speed testing compliance.

8. A backplane testing system, comprising:

a first test device that is configured to engage a first connector system on a backplane and that includes a loop back circuit;

a second test device that is configured to engage a second connector system on the backplane, wherein the second test device is configured to:

send a test signal through the second connector system such that the test signal is provided through at least one channel on the backplane and through the first connector system to the loop back circuit on the first test device; and

receive the test signal back through second connector system in response to the loop back circuit routing the test signal through the first connector system such that the test signal is provided through at least one channel on the backplane and through the second connector system; and

at least one analyzer subsystem that is configured to:

analyze the test signal that is received by the second test device to determine a testing compliance of the backplane.

9. The backplane testing system of claim 8 , wherein the backplane is a networking device backplane, the first connector system is a line module connector system, and the second connector system is a route processing module connector system.

10. The backplane testing system of claim 8 , wherein the first test device engages the first connector system that is configured to connect a plurality of devices to the backplane.

11. The backplane testing system of claim 8 , wherein the first test device engages a transmitter connection and a receiver connection on the first connector system to connect the transmitter connection and the receiver connection to the loop back circuit.

12. The backplane testing system of claim 8 , further comprising:

an analyzer system that is coupled to the second test device and that is configured to:

create the test signal that includes a pseudorandom binary sequence (PRBS) test pattern; and

analyze a received PRBS test pattern in the test signal that is received by the second test device to determine the testing compliance of the backplane.

13. The backplane testing system of claim 8 , wherein the testing compliance of the backplane is a speed testing compliance.

14. A method for testing a backplane, comprising:

sending, using a first test device, a test signal through a first connector system on a backplane such that the test signal is provided through at least one channel on the backplane;

receiving, using a second test device, the test signal through a second connector system on the backplane;

returning, using a loop back circuit in the second test device, the test signal through the second connector system and at least one channel on the backplane;

receiving, using the first test device, the test signal back through first connector system; and

analyzing, using at least one analyzer subsystem that is coupled to the first test device, the test signal that is received using the first test device to determine a testing compliance of the backplane.

15. The method of claim 14 , wherein the backplane is a backplane, the first connector system is a route processing module connector system, and the second connector system is a line module connector system.

16. The method of claim 15 , wherein the second test device engages the second connector system that is configured to connect a plurality of devices to the backplane.

17. The method of claim 14 , wherein the second test device engages a transmitter connection and a receiver connection on the second connector system to connect the transmitter connection and the receiver connection to the loop back circuit.

18. The method of claim 14 , further comprising:

creating, by an analyzer system that is coupled to the first test device, the test signal that includes a pseudorandom binary sequence (PRBS) test pattern; and

analyzing, by the analyzer system, a received PRBS test pattern in the test signal that is received using the first test device to determine the testing compliance of the backplane.

19. The method of claim 14 , further comprising:

determining, by a testing system that is coupled to the first test device, eye details of the test signal that is received using the first test device.

20. The method of claim 14 , wherein the testing compliance of the backplane is a speed testing compliance.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (041829/0873) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0724 →
RELEASE OF SECURITY INTEREST AT REEL 041808 FRAME 0516 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL INTERNATIONAL, L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0573 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY INTEREST (NOTES) Recorded Feb 28, 2017
From: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 041829/0873 →
PATENT SECURITY INTEREST (CREDIT) Recorded Feb 24, 2017
From: DELL INTERNATIONAL, L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 041808/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2016
From: CHANDRA, UMESH; MAI, TIMOTHY THINH
To: DELL PRODUCTS L.P.
Reel/Frame 040312/0537 →
Continuity (2)
Continuation 14644867 · Mar 11, 2015
Related Publication 20170059656A1 · Mar 2, 2017