UNIFIED SHADOW REGISTER FILE AND PIPELINE ARCHITECTURE SUPPORTING SPECULATIVE ARCHITECTURAL STATES
A method for supporting architecture speculation in a microprocessor is disclosed. The method comprises maintaining two registers for a register file entry, wherein a first one of the two registers supports a shadow register state for speculative instructions and a second one of the two registers supports a committed register state for committed instructions. The method also comprises reading a valid entry for supporting speculative execution from one of the two registers responsive to a read request event.
1 . A method for supporting architecture speculation in a microprocessor, the method comprising:
maintaining two registers for a register file entry, wherein a first one of the two registers supports a shadow register state for speculative instructions and a second one of the two registers supports a committed register state for committed instructions; and
responsive to a read request event, reading a valid entry for supporting speculative execution from one of the two registers.
2 . The method of claim 1 , wherein the reading is based on a value of two bits stored for the register file entry in an entry selector buffer.
3 . The method of claim 2 , further comprising:
updating the entry selector buffer when the shadow register state is ready for committing to allow valid results to be read from an appropriate one of the two registers.
4 . The method of claim 3 , further comprising:
in response to the updating, allowing speculative execution results to be rolled back to a most recent commit point in a pipeline of the microprocessor in case of an exception.
5 . The method of claim 2 , further comprising:
responsive to an instruction event, changing a state of the two bits stored in the entry selector buffer.
6 . The method of claim 2 , wherein the committed instructions cause a bit transition in the entry selector buffer after they have reached a commit stage in a pipeline of the microprocessor.
7 . The method of claim 1 , wherein execution in a pipeline of the microprocessor can proceed in the shadow register state without affecting the committed register state.
8 . A method for supporting architecture speculation in a microprocessor, the method comprising:
maintaining two registers for a register file entry, wherein a first one of the two registers supports a shadow register state for speculative instructions and a second one of the two registers supports a committed register state for committed instructions, wherein each of the two registers is maintained in discrete portions of a unified register file; and
responsive to a read request event, reading a valid entry for supporting speculative execution from one of the two registers.
9 . The method of claim 8 , wherein the reading is based on a value of two bits stored for the register file entry in an entry selector buffer.
10 . The method of claim 9 , further comprising:
updating the entry selector buffer when the shadow register state is ready for committing to allow valid results to be read from an appropriate one of the two registers.
11 . The method of claim 10 , further comprising:
in response to the updating, allowing speculative execution results to be rolled back to a most recent commit point in a pipeline of the microprocessor in case of an exception.
12 . The method of claim 9 , further comprising:
responsive to an instruction event, changing a state of the two bits stored in the entry selector buffer.
13 . The method of claim 9 , wherein the committed instructions cause a bit transition in the entry selector buffer after they have reached a commit stage in a pipeline of the microprocessor.
14 . The method of claim 8 , wherein execution in a pipeline of the microprocessor can proceed in the shadow register state without affecting the committed register state.
15 . A microprocessor coupled to a memory, wherein the memory has computer readable instructions which when executed by the microprocessor cause the microprocessor to implement a method for supporting architecture speculation, the method comprising:
maintaining two registers for a register file entry, wherein a first one of the two registers supports a shadow register state for speculative instructions and a second one of the two registers supports a committed register state for committed instructions; and
responsive to a read request event, reading a valid entry for supporting speculative execution from one of the two registers.
16 . The microprocessor of claim 15 , wherein the reading is based on a value of two bits stored for the register file entry in an entry selector buffer.
17 . The microprocessor of claim 16 , wherein the method further comprises:
updating the entry selector buffer when the shadow register state is ready for committing to allow valid results to be read from an appropriate one of the two registers.
18 . The microprocessor of claim 17 , wherein the method further comprises:
in response to the updating, allowing speculative execution results to be rolled back to a most recent commit point in a pipeline of the microprocessor in case of an exception.
19 . The microprocessor of claim 16 , wherein the method further comprises:
responsive to an instruction event, changing a state of the two bits stored in the entry selector buffer.
20 . The microprocessor of claim 16 , wherein the committed instructions cause a bit transition in the entry selector buffer after they have reached a commit stage in a pipeline of the microprocessor.