Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor

1. A method for translating instructions for a processor, comprising:

accessing a plurality of guest instructions that comprise multiple guest branch instructions;

assembling the plurality of guest instructions into a guest instruction block based on predicting outcomes of far branches while not predicting outcomes of near branches;

translating the guest instruction block into a corresponding native conversion block;

storing a mapping of the guest instruction block to corresponding native conversion block in a conversion look aside buffer; and

upon a subsequent request for a guest instruction, indexing the conversion look aside buffer to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in a native cache.

2. The method of claim 1 , further comprising:

forwarding the converted native instruction for execution in response to the hit.

3. The method of claim 1 , wherein a hardware fetch logic component fetches the plurality of guest instructions independent of the processor.

4. The method of claim 1 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered mappings of guest instruction blocks to corresponding native conversion blocks stored therein.

5. The method of claim 1 , wherein a conversion buffer is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer.

6. The method of claim 5 , wherein the conversion buffer is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer and the conversion look aside buffer.

7. The method of claim 1 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

8. The method of claim 1 , further comprising:

storing the native conversion block into the native cache.

9. A system for translating instructions for a processor, comprising:

a guest fetch logic component for accessing a plurality of guest instructions that comprise multiple guest branch instructions;

a guest fetch buffer for assembling the plurality of guest instructions into a guest instruction block based on predicting outcomes of far branches while not predicting outcomes of near branches;

a plurality of conversion tables for translating the guest instruction block into a corresponding native conversion block; and

a conversion look aside buffer for storing a mapping the guest instruction block to corresponding native conversion block in a conversion look aside buffer,

wherein the conversion look aside buffer is indexable to determine whether a hit occurred for a guest instruction, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in a native cache.

10. The system of claim 9 , wherein the converted native instruction is forwarded for execution in response to the hit.

11. The system of claim 9 , wherein a hardware fetch logic component fetches the plurality of guest instructions independent of the processor.

12. The system of claim 9 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered mappings stored therein.

13. The system of claim 9 , wherein a conversion buffer is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer.

14. The system of claim 13 , wherein the conversion buffer is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer and the conversion look aside buffer.

15. The system of claim 9 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

16. A microprocessor that implements a method of translating instructions, said microprocessor comprises:

a microprocessor pipeline;

a hardware accelerator module coupled to the microprocessor pipeline, wherein the hardware accelerator module further comprises:

a guest fetch logic component for accessing a plurality of guest instructions that comprise multiple guest branch instructions;

a guest fetch buffer for assembling the plurality of guest instructions into a guest instruction block based on predicting outcomes of far branches while not predicting outcomes of near branches;

a plurality of conversion tables for translating the guest instruction block into a corresponding native conversion block; and

a conversion look aside buffer for storing a mapping the guest instruction block to corresponding native conversion block in a conversion look aside buffer,

wherein the conversion look aside buffer is indexable to determine whether a hit occurred for a guest instruction, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in a native cache.

17. The microprocessor of claim 16 , wherein the converted native instruction is forwarded for execution in response to the hit.

18. The microprocessor of claim 16 , wherein a hardware fetch logic component fetches the plurality of guest instructions independent of the microprocessor.

19. The microprocessor of claim 16 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered native conversion blocks stored therein.

20. The microprocessor of claim 16 , wherein a conversion buffer is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer.