ALLOCATION OF AN INTERCONNECT STRUCTURE COMPRISING SHARED BUSES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES
A method for allocation of a shared interconnect structure in an integrated circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. The method also comprises contending for the plurality of resources in accordance with requests from the plurality of resource consumers. Finally, the method comprises accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of shared interconnect structures, wherein each shared interconnect structure is shared by each of a sender and each of a receiver.
1 . A method for allocation of a shared interconnect structure in an integrated circuit, the method comprising:
receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences;
contending for the plurality of resources in accordance with requests from the plurality of resource consumers; and
accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of shared interconnect structures, wherein each shared interconnect structure is shared by each of a sender and each of a receiver.
2 . The method of claim 1 , wherein the plurality of resources can be selected from a group consisting of: memory fragments of each of the engines, register file segments of each of the engines, read/write ports into memory fragments and register file segments of each of the engines and buses of the global interconnect structure.
3 . The method of claim 1 , wherein the plurality of resource consumers comprise at least one of execution units or address calculation units of each of the engines.
4 . The method of claim 1 , wherein the sender comprises an execution unit of an engine.
5 . The method of claim 1 , wherein a receiver can be selected from a group consisting of: memory fragments of each of the engines and register file segments of each of the engines.
6 . The method of claim 1 , further comprising:
issuing requests from the sender to a reservation adder and a threshold limiter at a requested resource.
7 . The method of claim 6 , further comprising:
at the requested resource, adding a number of requests for access to said each resource using the reservation adder;
at the requested resource, comparing the number of requests against the threshold limiter;
at the requested resource, canceling a subsequent request that exceeds the threshold limiter; and
at the requested resource, implementing requests that are not canceled.
8 . In a microprocessor, a method for allocation of a shared interconnect structure in an integrated circuit, the method comprising:
receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences;
contending for the plurality of resources in accordance with requests from the plurality of resource consumers; and
accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure comprises a plurality of shared interconnect structures, wherein each shared interconnect structure is shared by each of a sender and each of a receiver.
9 . The method of claim 8 , wherein the plurality of resources can be selected from a group consisting of: memory fragments of each of the engines, register file segments of each of the engines, read/write ports into memory fragments and register file segments of each of the engines and buses of the global interconnect structure.
10 . The method of claim 8 , wherein the plurality of resource consumers comprise at least one of execution units or address calculation units of each of the engines.
11 . The method of claim 8 , wherein the sender comprises an execution unit of an engine.
12 . The method of claim 8 , wherein a receiver can be selected from a group consisting of: memory fragments of each of the engines and register file segments of each of the engines.
13 . The method of claim 8 , further comprising:
issuing requests from the sender to a reservation adder and a threshold limiter at a requested resource.
14 . The method of claim 13 , further comprising:
at the requested resource, adding a number of requests for access to said each resource using the reservation adder;
at the requested resource, comparing the number of requests against the threshold limiter;
at the requested resource, canceling a subsequent request that exceeds the threshold limiter; and
at the requested resource, implementing requests that are not canceled.
15 . A microprocessor, comprising:
a plurality of resources having data for supporting execution of multiple code sequences;
a plurality of partitionable engines for implementing the execution of the multiple code sequences;
a plurality of resource consumers within each of the plurality of partitionable engines;
a global interconnect structure for coupling the plurality of resource consumers with the plurality of resources to access the data and execute the multiple code sequences, wherein the global interconnect structure comprises a plurality of shared interconnect structures, wherein each shared interconnect structure is shared by each of a sender and each of a receiver.
16 . The microprocessor of claim 15 , wherein the plurality of resources can be selected from a group consisting of: memory fragments of each of the engines, register file segments of each of the engines, read/write ports into memory fragments and register file segments of each of the engines and buses of the global interconnect structure.
17 . The microprocessor of claim 15 , wherein the plurality of resource consumers comprise at least one of execution units or address calculation units of each of the engines.
18 . The microprocessor of claim 15 , wherein the sender comprises an execution unit of an engine.
19 . The microprocessor of claim 15 , wherein a receiver can be selected from a group consisting of: memory fragments of each of the engines and register file segments of each of the engines.
20 . The microprocessor of claim 15 , wherein the plurality of resources comprises ports of a receiver.