Semiconductor device gate structure and method of fabricating thereof
A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
1. A method of forming a gate structure of a semiconductor device, comprising:
depositing a high-k dielectric layer over a substrate;
forming a dummy metal layer over the high-k dielectric layer, wherein the dummy metal layer includes fluorine and one of aluminum, titanium, or tantalum;
driving fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer;
removing the dummy metal layer after the driving the fluorine;
forming at least one work function layer over the passivated high-k dielectric layer; and
forming a fill metal layer over the at least one work function layer.
2. The method of claim 1 , further comprising:
forming a metal nitride layer over the high-k dielectric layer underlying the dummy metal layer.
3. The method of claim 2 , further comprising:
prior to forming the metal nitride layer, forming another metal nitride layer over the high-k dielectric.
4. The method of claim 1 , further comprising:
forming a gate contact over the fill metal layer.
5. The method of claim 1 , wherein the forming the dummy metal layer further includes forming a blocking layer over the dummy metal layer; and wherein the removing the dummy metal layer includes removing the blocking layer.
6. The method of claim 5 , wherein the forming the blocking layer includes depositing TiN.
7. The method of claim 1 , further comprising:
forming a dummy gate structure over the substrate; and
removing the dummy gate structure to form a trench, wherein the forming the dummy metal layer and forming the at least one work function layer are performed within the trench.
8. The method of claim 7 , wherein the forming the fill metal layer over the at least one work function layer includes filling the trench.
9. The method of claim 1 , wherein the driving fluorine from the dummy metal layer into the high-k dielectric layer includes performing an anneal process.
10. The method of claim 1 , wherein the dummy metal layer is one of AlF 3 or TiF 4 .
11. A method of forming a semiconductor device, comprising:
depositing a high-k dielectric layer over a substrate;
forming a metal nitride layer over the high-k dielectric layer, wherein the metal nitride comprising a composition including a first metal M 1 ;
forming a dummy layer over the metal nitride layer, wherein the dummy layer includes a composition comprising a second metal M 2 and fluorine F, wherein M 2 is a different metal than M 1 ;
performing a high temperature process driving fluorine F from the dummy layer into the high-k dielectric layer;
modifying the metal nitride layer to form a metal alloy layer including M 1 and M 2 ;
removing the dummy metal layer after the performing the high temperature process;
forming at least one work function layer over the metal alloy layer; and
forming a fill metal layer over the at least one work function layer.
12. The method of claim 11 , wherein the metal alloy layer provides a work function for a gate including the fill metal layer, the at least one work function layer, the metal alloy layer, and the high-k dielectric layer.
13. The method of claim 11 , further comprising:
forming a capping layer over the high-k dielectric layer and under the metal nitride layer.
14. The method of claim 13 , wherein the forming the capping layer includes depositing a titanium nitride composition.
15. The method of claim 11 , wherein the forming the dummy layer includes performing at least one of an atomic layer deposition (ALD) and a chemical vapor deposition (CVD) process directly on the metal nitride layer.
16. The method of claim 11 , wherein the forming the dummy layer includes depositing one of aluminum, tantalum, or titanium as M 2 .
17. A method of forming a gate structure of a semiconductor device, comprising:
depositing a gate dielectric layer over a substrate;
forming a dummy metal layer over the gate dielectric layer, wherein the dummy metal layer includes a metal of aluminum, titanium, or tantalum and fluorine;
performing an anneal driving fluorine from the dummy metal layer into the gate dielectric layer;
removing the dummy metal layer after the performing the anneal; and
after the removing, forming at least one work function layer over the gate dielectric layer.
18. The method of claim 17 , further comprising:
forming a tantalum nitride layer over the gate dielectric layer and underlying the dummy metal layer.
19. The method of claim 18 , wherein the tantalum nitride layer is transformed to a tantalum alloy layer including tungsten during the anneal.
20. The method of claim 19 , wherein the forming that least one work function layer includes forming that at least one work function layer on the tantalum alloy layer.