Randomized compiling for quantum computation

1. An error reduction method comprising:

defining a set of gate types that consist of a first subset of gate types and a second subset of gate types;

receiving an initial quantum-logic gate sequence at a first computer system, wherein each gate in the initial quantum-logic gate sequence is a gate type in the first subset of gate types or a gate type in the second subset of gate types and wherein the initial quantum-logic gate sequence includes at least one gate that is a gate type in the second subset of gate types;

generating, by operation of the first computer system, a modified quantum-logic gate sequence by applying a plurality of virtual random gates to the initial quantum-logic gate sequence, wherein

the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence,

the initial quantum-logic gate sequence comprises a series of cycles,

the modified quantum-logic gate sequence includes a corresponding cycle for each cycle in the series of cycles of the initial quantum-logic gate sequence,

the modified quantum-logic gate sequence is generated by applying one or more virtual random gates in the plurality of virtual random gates in each cycle of the initial quantum-logic gate sequence,

after an initial cycle in the series of cycles, a portion of the plurality of virtual random gates applied in each cycle are configured to invert one or more of the virtual random gates applied in a preceding cycle in the series of cycles, and

each respective gate that is a gate type in the second subset of gate types in the initial quantum-logic gate sequence is preserved in the respective cycle in the modified quantum-logic gate sequence that corresponds to the cycle in the initial quantum-logic gate sequence in which the respective gate occurred,

providing the modified quantum-logic gate sequence to the quantum information processor through an interface between the first computer system and the quantum information processor; and

executing the modified quantum-logic gate sequence on the quantum information processor, wherein execution of the modified quantum-logic gate sequence on the quantum information incurs reduced error relative to execution of the initial quantum-logic gate sequence by converting coherent error, arising in the quantum information processor upon execution of the initial quantum-logic gate sequence, into stochastic error in the quantum information processor.

2. The error reduction method of claim 1 , wherein the plurality of virtual random gates comprises virtual random Pauli gates or dihedral gates.

3. The error reduction method of claim 1 , wherein providing the modified quantum-logic gate sequence to be executed by the quantum information processor comprises converting the modified quantum-logic gate sequence into machine code that is executable by the quantum information processor.

4. The error reduction method of claim 1 , wherein the initial quantum-logic gate sequence comprises a bare quantum-logic circuit.

5. The error reduction method of claim 1 , wherein the executing the modified quantum-logic gate sequence obtains a set of outcomes that are averaged.

6. The error reduction method of claim 1 , wherein

the initial quantum-logic gate sequence comprises a bare quantum-logic circuit,

the plurality of virtual random gates comprises virtual twirling gates and virtual correction gates.

7. The error reduction method of claim 6 , wherein the virtual twirling gates and the virtual correction gates are applied to individual cycles in the series of cycles.

8. The error reduction method of claim 7 , wherein, after an initial cycle, the virtual correction gates applied in each cycle are configured to invert corresponding virtual twirling gates applied in a preceding cycle.

9. The error reduction method of claim 1 , wherein

the first set of gates comprises the Pauli gates and the phase gate R, and

the second of gates comprises the Hardamard gate H, the π/8 gate √{square root over (R)}and the two-qubit controlled Z-gate Δ(Z).

10. A system comprising:

a first computer system comprising a memory and a processor;

a quantum device comprising a quantum information processor; and

an interface between the first computer system and the quantum information processor;

wherein the memory comprises one or more programs that use the processor of the first computer system to perform operations comprising:

receiving an initial quantum-logic gate sequence at the first computer system, wherein each gate in the initial quantum-logic gate sequence is a gate type in a set of gate types that consist of a first subset of gate types and a second subset of gate types and wherein the initial quantum-logic gate sequence includes at least one gate that is a gate type in the second subset of gate types,

generating a modified quantum-logic gate sequence by applying a plurality of virtual random gates to the initial quantum-logic gate sequence, wherein

the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence;

the initial quantum-logic gate sequence comprises a series of cycles,

the modified quantum-logic gate sequence includes a corresponding cycle for each cycle in the series of cycles of the initial quantum-logic gate sequence,

the modified quantum-logic gate sequence is generated by applying one or more virtual random gates in the plurality of virtual random gates in each cycle of the initial quantum-logic gate sequence,

after an initial cycle in the series of cycles, a portion of the plurality of virtual random gates applied in each cycle are configured to invert one or more of the virtual random gates applied in a preceding cycle in the series of cycles, and

each respective gate that is a gate type in the second subset of gate types in the initial quantum-logic gate sequence is preserved in the respective cycle in the modified quantum-logic gate sequence that corresponds to the cycle in the initial quantum-logic gate sequence in which the respective gate occurred;

providing the modified quantum-logic gate sequence to the quantum information processor through the interface; wherein

the quantum device executes the modified quantum-logic gate sequence on the quantum information processor, thereby incurring a reduced error relative to execution of the initial quantum-logic gate sequence, by converting coherent error, arising in the quantum information processor upon execution of the initial quantum-logic gate sequence, into stochastic error in the quantum information processor.

11. The system of claim 10 , wherein the plurality of virtual random gates comprises virtual random Pauli gates or dihedral gates.

12. The system of claim 10 , wherein providing the modified quantum-logic gate sequence to be executed by the quantum information processor comprises converting the modified quantum-logic gate sequence into machine code that is executable by the quantum information processor.

13. The system of claim 10 , wherein the initial quantum-logic gate sequence comprises a bare quantum-logic circuit.

14. The system of claim 10 , wherein the executing the modified quantum-logic gate sequence obtains a set of outcomes that are averaged.

15. The system of claim 10 , wherein

the initial quantum-logic gate sequence comprises a bare quantum-logic circuit,

the plurality of virtual random gates comprises virtual twirling gates and virtual correction gates.

16. The system of claim 15 , wherein the virtual twirling gates and the virtual correction gates are applied to individual cycles in the series of cycles.

17. The system of claim 16 , wherein, after an initial cycle, the virtual correction gates applied in each cycle are configured to invert corresponding virtual twirling gates applied in a preceding cycle.

18. The system of claim 10 , wherein

the first set of gates comprises the Pauli gates and the phase gate R, and

the second of gates comprises the Hardamard gate H, the π/8 gate √{square root over (R)}and the two-qubit controlled Z-gate Δ(Z).