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View Patent ↗A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.
1. A system to implement a multiple thread architecture, the system comprising:
an execution bucket; and
a register file hierarchy configured to support high bandwidth small capacity register files adjacent the execution bucket and lower bandwidth and larger capacity register files removed from the execution bucket, wherein the register file hierarchy includes a level that is configured to store virtual copies of a register set that is supported by an instruction set architecture for a plurality of contexts.
2. The system of claim 1 , further comprising:
a thread allocation pointer array coupled to the execution bucket, the thread allocation pointer array to store pointers to a set of buckets that a thread is allowed to place blocks of instructions into.
3. The system of claim 1 , further comprising:
a bucket retirement array coupled to the execution bucket, the bucket retirement array to store a retirement thread point that is incremented to a next bucket in the execution bucket upon retirement of each bucket.
4. The system of claim 1 , wherein the register file hierarchy includes the register set that is supported by the instruction set architecture.
5. A system to support a context switch architecture, the system comprising:
context switch circuitry to support capture of current state information; and
a context storage mechanism configured to simultaneously store a portion of the current state information and a portion of previous state information during an incremental context switch.
6. The system of claim 5 , wherein the context storage mechanism is a last in first out (LIFO) storage mechanism.
7. The system of claim 5 , wherein the context switch circuitry switches registers that are not shared amongst multiple threads.
8. The system of claim 7 , wherein the context switch circuitry maintaining registers that are shared between multiple threads during a context switch.
9. The system of claim 7 , wherein a register is context switched when a next context attempts to access the register and the register contains an old context.
10. The system of claim 7 , wherein multiple registers with a same register number from different contexts are differentiated by a context identifier.
11. The system of claim 7 , wherein registers associated with static threads are not updated during a context switch.
12. The system of claim 11 , wherein registers associated with dynamic threads are updated during a context switch.