Scan Logic For Circuit Designs With Latches And Flip-Flops
A system for scanning a circuit includes flip-flops and latches includes a multiplexer to couple an output of a flip-flop with an input of a latch. The multiplexer has an input receiving an input signal for the latch and another input coupled with output of the flip-flop. The system further another multiplexer to couple output of the first multiplexer with an input of another flip-flop. The system also includes scan logic for controlling multiplexers to load test data into the flip-flop and into the latch from the flip-flop. The system also includes scan logic for passing output of the flip-flop and the latch into portions of the circuit to be tested.
1 . A method for scanning a circuit comprising a plurality of flip-flops and latches, the method comprising:
providing a first multiplexer to couple an output of a first flip-flop with an input of a first latch, wherein the first multiplexer has a first input receiving an input signal for the first latch and a second input coupled with output of the first flip-flop;
providing a second multiplexer to couple output of the first multiplexer with an input of a second flip-flop;
controlling the first and second multiplexers to load test data into the first flip-flop and into the first latch from the first flip-flop; and
passing output of the first flip-flop and the first latch into portions of the circuit to be tested.
2 . The method according to claim 1 , wherein the first flip-flop acts as a lock-up latch for the first latch.
3 . The method according to claim 1 , wherein the first flip-flop and the first latch receive separate scan clock signals.
4 . The method according to claim 1 , wherein the first multiplexer and the second multiplexer receive separate enable signals.
5 . The method according to claim 1 , further comprising routing a first circuit logic to an input of the first multiplexer, wherein the first circuit logic is configured to provide a signal to the latch during non-scanning operation.
6 . The method according to claim 5 , further comprising loading result data from the first flip-flop and the first latch, the result data to indicate processing of test data by the first circuit logic.
7 . The method according to claim 1 , further comprising capturing first result data from the first flip-flop reflecting performance of the circuit to be tested.
8 . The method according to claim 7 , further comprising, after capturing the first result data from the first flip-flop, loading the same test data back into the first flip-flop.
9 . The method according to claim 8 , further comprising, after loading the same test data back into the first flip-flop, capturing second result data from the first latch reflecting performance of the circuit to be tested and storing the second result data into the first flip-flop.
10 . The method according to claim 9 , further comprising, after storing the second result data into the first flip-flop, simultaneously shifting out the second result data and shifting in new test data to the first flip-flop.
11 . A system for scanning a circuit comprising a plurality of flip-flops and latches, the system comprising:
a first multiplexer configured to couple an output of a first flip-flop with an input of a first latch, wherein the first multiplexer has a first input for receiving an input signal for the first latch and a second input coupled with output of the first flip-flop;
a second multiplexer configured to couple output of the first multiplexer with an input of a second flip-flop; and
scan logic configured to:
control the first and second multiplexers to load test data into the first flip-flop and into the first latch from the first flip-flop; and
pass output of the first flip-flop and the first latch into portions of the circuit to be tested.
12 . The system according to claim 11 , wherein the first flip-flop is configured to perform as a lock-up latch for the first latch.
13 . The system according to claim 11 , wherein the first flip-flop and the first latch are configured to receive separate scan clock signals.
14 . The system according to claim 11 , wherein the first multiplexer and the second multiplexer are configured to receive separate enable signals.
15 . The system according to claim 11 , wherein the scan logic is further configured to route a first circuit logic coupled to an input of the first multiplexer, wherein the first circuit logic is configured to provide a signal to the latch during non-scanning operation.
16 . The system according to claim 15 , wherein the scan logic is further configured to cause loading of result data from the first flip-flop and the first latch, the result data to indicate processing of test data by the first circuit logic.
17 . The system according to claim 11 , wherein the scan logic is further configured to route capturing first result data from the first flip-flop reflecting performance of the circuit to be tested.
18 . The system according to claim 17 , wherein the scan logic is further configured to cause, after capturing the first result data from the first flip-flop, loading the same test data back into the first flip-flop.
19 . The system according to claim 18 , wherein the scan logic is further configured to cause, after loading the same test data back into the first flip-flop, capturing second result data from the first latch reflecting performance of the circuit to be tested and storing the second result data into the first flip-flop.
20 . The system according to claim 19 , wherein the scan logic is further configured to cause, after storing the second result data into the first flip-flop, simultaneously shifting out the second result data and shifting in new test data to the first flip-flop.