Semiconductor integrated circuit capable of precisely adjusting delay amount of strobe signal
An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal (CK) and receives a data signal (DQ) and a strobe signal (DQS) from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal (DQS). The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal (DQS) in a plurality of steps in accordance with the set frequency of the clock signal (CK). The second adjustment circuit is capable of adjusting the delay amount of the strobe signal (DQS) with a higher precision than the first adjustment circuit.
1. A semiconductor device comprising an interface circuit,
the interface circuit comprising:
a buffer configured to receive a data signal and a strobe signal from an external memory device;
a delay circuit configured to delay the received strobe signal; and
a data detection circuit configured to sample the data signal at a timing of an edge of the strobe signal having been delayed by the delay circuit,
the delay circuit comprising:
a first adjustment circuit including a plurality of delay elements and configured to adjust a delay amount of the strobe signal in a plurality of steps; and
a second adjustment circuit connected in series with the first adjustment circuit and capable of adjusting the delay amount of the strobe signal with a higher precision than the first adjustment circuit,
the first adjustment circuit further comprising:
a bypass line connected in parallel with a part of the plurality of delay elements and having a delay amount smaller than a delay amount of the part of the delay elements as a whole with which the bypass line is connected in parallel; and
a selector configured to select and output the strobe signal passing through the part of the plurality of delay elements or the strobe signal passing through the bypass line connected in parallel with the part of the plurality of delay elements, wherein
the plurality of delay elements provided in the first adjustment circuit are connected in series with each other, and divided into M blocks from first to M-th blocks each including a plurality of delay elements,
the bypass line is connected in parallel with each of the M blocks,
the selector is provided for each of the M blocks, and configured to select the strobe signal passing through an associated i-th block of the M blocks (1≦i≦M) or the strobe signal passing through the bypass line connected in parallel with the i-th M block, and
the semiconductor device further comprises a clock generator configured to generate a clock signal having a set frequency,
the interface circuit is configured to supply an operation clock to the external memory device based on the clock signal, and
the first adjustment circuit further comprises a selection circuit configured to select, in accordance with the set frequency of the clock signal, one of outputs of the selectors which are associated with the respective M blocks.
2. The semiconductor device according to claim 1 , further comprising:
a central processing unit configured to set the frequency of the clock signal; and
a control circuit configured to output a delay-amount setting value corresponding to the set frequency of the clock signal, wherein
the selection circuit is configured to select, based on the delay-amount setting value, one of outputs of the selectors which are associated with the respective M blocks.
3. The semiconductor device according to claim 2 , wherein
the control circuit is configured to determine the delay-amount setting value so that a number of delay elements through which the strobe signal passes is larger as the set frequency is lower.
4. A semiconductor device comprising an interface circuit,
the interface circuit comprising:
a buffer configured to receive a data signal and a strobe signal from an external memory device;
a delay circuit configured to delay the received strobe signal; and
a data detection circuit configured to sample the data signal at a timing of an edge of the strobe signal having been delayed by the delay circuit,
the delay circuit comprising:
a first adjustment circuit including a plurality of delay elements and configured to adjust a delay amount of the strobe signal in a plurality of steps; and
a second adjustment circuit connected in series with the first adjustment circuit and capable of adjusting the delay amount of the strobe signal with a higher precision than the first adjustment circuit, and
the first adjustment circuit further comprising:
a bypass line connected in parallel with a part of the plurality of delay elements and having a delay amount smaller than a delay amount of the part of the delay elements as a whole with which the bypass line is connected in parallel; and
a selector configured to select and output the strobe signal passing through the part of the plurality of delay elements or the strobe signal passing through the bypass line connected in parallel with the part of the plurality of delay elements, wherein
the plurality of delay elements provided in the first adjustment circuit are connected in series with each other, and divided into M blocks from first to M-th blocks each including a plurality of delay elements,
the bypass line is connected in parallel with at least one of the M blocks,
the selector is provided for the bypass line, and configured to select the strobe signal passing through the at least one of the M blocks or the strobe signal passing through the bypass line connected in parallel with the at least one of the M blocks, and
the semiconductor device further comprises a clock generator configured to generate a clock signal having a set frequency,
the interface circuit is configured to supply an operation clock to the external memory device based on the clock signal, and
the first adjustment circuit further comprises a selection circuit configured to select, in accordance with the set frequency of the clock signal, one of outputs of the selectors which are associated with the part of the M blocks.