MOSFET AND A METHOD FOR MANUFACTURING THE SAME

1 . A metal-oxide semiconductor field-effect transistor (MOSFET), wherein:

a well region of the second conductivity type is formed in the surface of the semiconductor substrate;

a gate dielectric layer and a polysilicon gate are sequentially formed on the surface of said well region;

a doped source region of the first conductivity type and a doped drain region of the first conductivity type are respectively formed in the surface of said well region;

the drain region is self-aligned with a first side of said polysilicon gate, and said source region is self-aligned with a second side of said polysilicon gate;

the source region and said drain region are unsymmetrical in structure, wherein the horizontal junction width of said drain region is greater than that of said source region, and the vertical junction depth of said drain region is greater than that of said source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of said drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of said source region;

the gate dielectric layer is unsymmetrical in structure, wherein said gate dielectric layer includes a first gate dielectric section and a second gate dielectric section which are horizontally connected; the thickness of said first gate dielectric section is greater than that of said second gate dielectric section; horizontally, said drain region extends beyond the first side of said polysilicon gate to the bottom of said polysilicon gate, thereby forming an overlap between said drain region and said polysilicon gate, with said first gate dielectric section located therein; and the GIDL effect in the device can be reduced by increasing the thickness of said first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of said second gate dielectric section.

2 . The MOSFET of claim 1 , wherein said semiconductor substrate is a silicon substrate.

3 . The MOSFET of claim 1 , wherein said source region is formed by a heavily doped source/drain implanted region having the first conductivity type, said drain region is formed by an overlap between the heavily doped source/drain implanted region and a lightly doped drain region having the first conductivity type, the source/drain implanted region of said source region and the source/drain implanted region of said drain region are formed by the same process, and the junction depth of said drain region is adjusted through said lightly doped drain region.

4 . The MOSFET of claim 1 , wherein said gate dielectric layer is a gate oxide layer.

5 . The MOSFET of claim 4 , wherein said second gate dielectric section is a thermal oxide layer or deposited oxide layer, and said first gate dielectric section adds a local oxide layer to said second gate dielectric section.

6 . The MOSFET of claim 1 , wherein side walls are formed on the sides of said polysilicon gate.

7 . The MOSFET of claim 1 , wherein the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

8 . A method of manufacturing the MOSFET, comprising the steps of:

step 1: providing a semiconductor substrate and introducing dopant having the second conductivity type in the surface thereof to form a well region;

step 2: forming a first oxide layer on the surface of said semiconductor substrate by thermal oxidation or chemical vapor deposition;

step 3: forming a polysilicon gate on the surface of the first oxide layer by chemical vapor deposition and photolithography, wherein said polysilicon gate covers the surface of said well region via said first oxide layer;

step 4: forming a first dielectric layer by chemical vapor deposition, wherein said first dielectric layer is made of silicon nitride or silicon oxynitride;

step 5: removing said first dielectric layer in the drain-forming region with photolithography and etching processes, while retaining said first dielectric layer in the source-forming region, wherein said drain-forming region is located outside a first side of said polysilicon gate, said source-forming region is located outside a second side of said polysilicon gate, the reserved part of said first dielectric layer further extends from said source-forming region to the top of said polysilicon gate, and the removed part of said first dielectric layer further extends from said drain-forming region to the top of said polysilicon gate;

step 6: with the photoresist on said first dielectric layer and the top thereof as a mask, conducting ion implantation of dopants having the first conductivity type to form a lightly doped drain region, wherein said lightly doped drain region is self-aligned with the first side of said polysilicon gate; the junction depth of the drain region is adjusted through ion implantation of said lightly doped drain region; and horizontally, said lightly doped drain region extends from the first side of said polysilicon gate to the bottom thereof, thereby forming an overlap between said drain region and said polysilicon gate;

step 7: removing the photoresist on the top of said first dielectric layer, and with said first dielectric layer as a mask, performing local thermal oxidation to form a local thermal oxide layer, wherein said local thermal oxide layer extends from said drain-forming region to the bottom of said polysilicon gate, and then removing said first dielectric layer;

said first oxide layer located at the bottom of said polysilicon gate and not overlaid with said local thermal oxide layer constitutes a second gate dielectric section and the overlap between said local thermal oxide layer extending to the bottom of said polysilicon gate and said first oxide layer constitutes a first gate dielectric section;

said first gate dielectric section and said second gate dielectric section are connected horizontally to form a gate dielectric layer; said first gate dielectric section is located in the overlap between said drain region and said polysilicon gate; the GIDL effect in the device can be reduced by increasing the thickness of said first gate dielectric section, and the driving current of the device can be increased by reducing the thickness of said second gate dielectric section;

step 8: performing resource/drain implantation of impurity having the first conductivity type to form heavily doped resource/drain implanted regions on both sides of said polysilicon gate, wherein each said resource/drain implanted region is self-aligned with a corresponding side of said polysilicon gate, the overlap between said resource/drain implanted region on the first side of said polysilicon gate and said lightly doped drain region forms a drain region, and said resource/drain implanted region on the second side of said polysilicon gate forms a source region;

said source region and said drain region are unsymmetrical in structure, wherein the horizontal junction width of said drain region is greater than that of said source region, and the vertical junction depth of said drain region is greater than that of said source region; the breakdown voltage of the device can be raised by increasing the horizontal and vertical junction depths of said drain region, and the horizontal dimension of the device can be diminished by reducing the horizontal and vertical junction depths of said source region.

9 . The method of manufacturing a MOSFET of claim 8 , wherein said semiconductor substrate is a silicon substrate.

10 . The method of manufacturing the MOSFET of claim 8 , wherein prior to performing said source/drain implantation in Step 8, side walls are formed on the sides of said polysilicon gate by deposition and etching processes;

when performing said source/drain implantation, said side walls on the two sides of said polysilicon gate are taken as the boundaries for self-alignment, said source/drain implantation is performed at a tilt angle, said source/drain implanted regions formed thereby extend horizontally to the bottom of said side walls, and the breadth of the horizontal extension of said source/drain implanted regions is greater than the maximum horizontal breadth of said side walls.

11 . The method of manufacturing a MOSFET of claim 10 , wherein the angle between the ion beam and the vertical direction is greater than 10 degrees and the implantation dose exceeds 5E14 cm −2 in said source/drain implantation.

12 . The method of manufacturing a MOSFET of claim 8 , wherein the angle between the ion beam and the vertical direction is greater than 10 degrees and the implantation dose exceeds 5E14 cm −2 in said ion implantation of dopants to form a lightly doped drain region in Step 6.

13 . The method of manufacturing a MOSFET of claim 8 , wherein the thickness of said first dielectric layer is between 50 and 300 angstroms.

14 . The method of manufacturing a MOSFET of claim 8 , wherein the thickness of said local thermal oxide layer is between 30 and 300 angstroms.

15 . The method of manufacturing a MOSFET of claim 8 , wherein the MOSFET is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; alternatively, the MOSFET is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.