Base current compensation for a BJT current mirror

1. A current mirror circuit, comprising:

an input current leg including:

a first bipolar junction transistor (BJT) having a collector terminal configured to receive an input current sourced at a current node; and

a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the first BJT; and

a first output current leg including:

a second BJT having a collector terminal configured to supply an output current; and

a second MOSFET having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the second BJT.

2. The current mirror circuit of claim 1 , wherein the base terminal of the first BJT and the base terminal of the second BJT are connected by a circuit line having a parasitic resistance.

3. The current mirror circuit of claim 1 , wherein the second BJT is a variable BJT formed by a plurality of BJT devices coupled in parallel and selectively enabled by one or more digital control signals.

4. The current mirror circuit of claim 3 , wherein the second MOSFET is coupled to each one of the plurality of BJT devices of said variable BJT.

5. The current mirror of claim 1 , further comprising a second output current leg including:

a third BJT having a collector terminal configured to supply a further output current; and

a third MOSFET having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the third BJT.

6. The current mirror of claim 5 , wherein the first and second output current legs are connected together at a common output current node.

7. The current mirror of claim 6 , further comprising a precharge circuit configured to precharge the common output current node to a precharge voltage.

8. The current mirror of claim 1 , further comprising a first switch configured to selectively couple the gate terminal of the second MOSFET to the current node in response to a first control signal.

9. The current mirror of claim 8 , further comprising a second switch configured to selectively couple the gate terminal of the second MOSFET to the source terminal of the second MOSFET in response to a second control signal.

10. The current mirror of claim 9 , wherein the first and second control signals are non-overlapping.

11. The current mirror circuit of claim 1 , wherein the base terminal of the first BJT and the base terminal of the second BJT are connected by a circuit line having a parasitic resistance, and further comprising a third switch configured to selectively couple the base terminal of the second BJT to the circuit line in response to a third control signal.

12. The current mirror of claim 11 , further comprising a fourth switch configured to selectively couple the base terminal of the second BJT to the emitter terminal of the second BJT in response to a fourth control signal.

13. The current mirror of claim 12 , wherein the third and fourth control signals are non-overlapping.

14. The current mirror of claim 12 , further comprising a fifth switch configured to selectively couple the collector terminal of the second BJT to the emitter terminal of the second BJT in response to a fifth control signal.

15. The current mirror of claim 1 ,

wherein the input current leg further includes a first cascode transistor coupled in series with the first BJT to receive said input current sourced at said current node;

wherein the output current leg further includes a second cascode transistor coupled in series with the second BJT; and

wherein said first and second cascode transistors are biased by a bias voltage.

16. The current mirror of claim 15 , further comprising a sixth switch configured to selectively couple a control terminal of the second cascode transistor to the bias voltage in response to a sixth control signal.

17. The current mirror of claim 16 , further comprising a seventh switch configured to selectively couple the control terminal of the second cascode transistor to the second BJT in response to a seventh control signal.

18. The current mirror of claim 17 , wherein the sixth and seventh control signals are non-overlapping.