IP Library Granted Patent US 10,115,694
Granted Patent B2
US 10,115,694 · App. 15/368,732 · Granted Oct 30, 2018

Electronic device, electronic device fabrication method, and electronic apparatus

Inventors: Hidehiko Kira (Nagano, JP); Naoaki Nakamura (Kawasaki, JP); Sanae Iijima (Nagano, JP)
Assignee: FUJITSU LIMITED
H01L24/17H01L21/6838H01L21/78H01L23/295H01L23/3142H01L23/367H01L24/32H01L24/73H01L24/81H01L24/83H01L24/92H01L24/94H01L25/0657H01L25/50H01L2224/13109H01L2224/13111H01L2224/13113H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/16113H01L2224/16148H01L2224/16238H01L2224/2929H01L2224/29324H01L2224/29339H01L2224/29344H01L2224/29347H01L2224/29387H01L2224/73204H01L2224/75981H01L2224/81136H01L2224/81193H01L2224/81203H01L2224/81815H01L2224/831H01L2224/9211H01L2225/06513H01L2225/06589H01L2924/014H01L2924/04642H01L2924/05032H01L2924/0665H01L2924/0715
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Quick Facts
Patent No.
US 10,115,694
App. No.
15/368,732
Granted
Oct 30, 2018
Kind
B2
Abstract

An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity in a back surface, a filler placed in the concavity, and a flat plate placed over the back surface with the filler therebetween, and further includes a second substrate disposed on the first front surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a second front surface opposite the first front surface. The filler and flat plate minimize deformation of the first substrate and variation in the distance between the group of first terminals and the group of second terminals caused by the deformation of the first substrate, which thereby reduces the occurrence of a failure in bonding together the group of first terminals and the group of second terminals.

Claims (16)

1. An electronic device fabrication method comprising:

preparing an electronic part including:

a first substrate having first terminals over a first surface and having a concavity in a second surface opposite to the first surface;

a filler placed in the concavity; and

a flat plate placed over the second surface with the filler therebetween; and

making the first surface of the electronic part face a third surface of a second substrate having second terminals over the third surface and bonding the first terminals and the second terminals together,

the preparing the electronic part includes:

sucking and holding the first surface of the first substrate on a first sucking surface;

placing the filler in the concavity of the first substrate sucked and held; and

placing the flat plate over the second surface of the first substrate sucked and held with the filler therebetween.

2. The electronic device fabrication method according to claim 1 , wherein the bonding the first terminals and the second terminals together includes sucking and holding the flat plate of the electronic part on a second sucking surface and making the first surface face the third surface.

3. The electronic device fabrication method according to claim 1 , wherein the first substrate is a wafer including semiconductor elements.

4. The electronic device fabrication method according to claim 3 further comprising dicing the first substrate and the flat plate in positions in which the semiconductor elements of the first substrate are separated.

5. The electronic device fabrication method according to claim 3 further comprising, after the bonding the first terminals and the second terminals together, dicing the first substrate and the second substrate in positions in which the semiconductor elements of the first substrate are separated.

6. The electronic device fabrication method according to claim 1 , wherein the first substrate is a semiconductor element.

7. The electronic device fabrication method according to claim 1 , wherein the preparing the electronic part further includes forming over the first surface a resin layer which covers the first terminals.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Feb 21, 2025
From: JPMORGAN CHASE BANK, N.A.
To: GRAFTECH INTERNATIONAL HOLDINGS INC. (F/K/A AS UCAR CARBON COMPANY INC.)
Reel/Frame 070291/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2016
From: KIRA, HIDEHIKO; NAKAMURA, NAOAKI; IIJIMA, SANAE
To: FUJITSU LIMITED
Reel/Frame 040807/0631 →
Priority Claims (1)
JP 2015-253364 · Dec 25, 2015 · national
Continuity (1)
Related Publication 20170186718A1 · Jun 29, 2017