IP Library Granted Patent US 9,991,913
Granted Patent B1
US 9,991,913 · App. 15/371,768 · Granted Jun 5, 2018

Discrete levels envelope tracking

Inventors: Nati Dinur (Haifa, IL); Uri Perlmutter (Holon, IL); Michael Kerner (Tel Mond, IL)
Assignee: Intel IP Corporation
H04B1/0475H04L27/2628H04L27/32H04B2001/0408
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Quick Facts
Patent No.
US 9,991,913
App. No.
15/371,768
Granted
Jun 5, 2018
Kind
B1
Abstract

An envelope tracking arrangement is disclosed and includes a level select component, a chunk supply component and a power amplifier. The level select component is configured to segment an input signal into chunks based on time and to select a chunk level for each chunk based on information or envelope information. The chunk supply component is configured to selectively provide a discrete supply voltage according to the selected chunk level. The power amplifier is configured to generate a radio frequency (RF) output signal based on the input signal and utilizing the discrete supply voltage.

Claims (10)

1. An envelope tracking arrangement comprising:

a level select component configured to select a chunk length and a chunk level for a chunk of an input signal;

a digital pre-distortion (DPD) component configured to apply a distortion to the input signal using the selected chunk level to generate a pre-distorted signal;

a mixer configured to mix the pre-distorted signal at a selected frequency to generate a mixed signal; and

a power amplifier configured to generate a radio frequency (RF) output signal based on the mixed signal using a supply voltage at the selected chunk level for a discrete period of time, wherein the discrete period of time is the selected chunk length.

2. The arrangement of claim 1 , further comprising a supply component configured to provide the supply voltage at the selected chunk level.

3. The arrangement of claim 2 , further comprising a delay element configured to delay communication of the selected chunk level to the supply component by a path delay.

4. The arrangement of claim 1 , further comprising an inverse fast Fourier transform (IFFT) component configured to obtain symbols from the input signal.

5. The arrangement of claim 1 , wherein the DPD component includes a plurality of digital pre-distorters associated with varied voltages.

6. The arrangement of claim 1 , wherein the selected chunk level is one of a plurality of chunk levels.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053307/0500 →
CONFIRMATORY ASSIGNMENT Recorded Jun 25, 2020
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 053051/0139 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: DINUR, NATI; PERLMUTTER, URI; KERNER, MICHAEL
To: INTEL IP CORPORATION
Reel/Frame 042140/0564 →