Semiconductor memory apparatus and operating method
View Patent ↗A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.
1. A semiconductor memory apparatus comprising:
a first mat including a first bit line and a first word line;
a second mat including a second bit line and a second word line;
a first bit line driving circuit configured to enable the first bit line in response to at least one of a first bit line select signal and a first machine bit line select signal;
a second bit line driving circuit configured to enable the second bit line in response to at least one of a second bit line select signal and a second machine bit line select signal;
a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and
a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.
2. The semiconductor memory apparatus according to claim 1 , further comprising:
a sense amplifier configured to generate output data by sensing a voltage or current difference between the first bit line and the second bit line.
3. The semiconductor memory apparatus according to claim 1 , wherein the first bit line driving circuit enables the first bit line if at least one of the first bit line select signal and the first machine bit line select signal is enabled.
4. The semiconductor memory apparatus according to claim 1 , wherein the enabling of the first bit line includes the first bit line driving circuit providing a preset current or a voltage to the first bit line if at least one of the first bit line select signal and the first machine bit line select signal is enabled.
5. The semiconductor memory apparatus according to claim 1 , wherein the second bit line driving circuit enables the second bit line if at least one of the second bit line select signal and the second machine bit line select signal is enabled.
6. The semiconductor memory apparatus according to claim 1 , wherein the enabling of the second bit line includes the second bit line driving circuit providing a preset current or voltage to the second bit line if at least one of the second bit line select signal and the second machine bit line select signal is enabled.
7. The semiconductor memory apparatus according to claim 1 , wherein the state machine enables the second machine bit line select signal if the column-related decoding circuit enables the first bit line select signal in response to the column address.
8. The semiconductor memory apparatus according to claim 2 , wherein the column-related decoding circuit additionally generates a first column select signal and a second column select signal in response to the column address.
9. The semiconductor memory apparatus according to claim 8 , wherein the state machine additionally generates a first machine column select signal and a second machine column select signal in response to the column address.
10. The semiconductor memory apparatus according to claim 9 , further comprising:
a first switch configured to couple and decouple the first bit line and the sense amplifier in response to at least one of the first column select signal and the first machine column select signal; and
a second switch configured to couple and decouple the second bit line and the sense amplifier in response to at least one of the second column select signal and the second machine column select signal.