Circuit, logic circuit, processor, electronic component, and electronic device
View Patent ↗A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.
1. A circuit comprising;
first to sixth nodes;
first to third transistors;
a first capacitor; and
a first circuit,
wherein the first capacitor is electrically connected to the first node,
wherein the first transistor is configured to control electrical continuity between the first node and the second node,
wherein the second transistor is configured to control electrical continuity between the first node and the third node,
wherein the third transistor is configured to control electrical continuity between the third node and the fourth node,
wherein a gate of the third transistor is electrically connected to the fifth node,
wherein a gate of the second transistor is electrically connected to the sixth node,
wherein the fifth node is electrically connected to the first circuit, and
wherein the first circuit is configured to input voltage higher than voltage of the fifth node to a gate of the first transistor.
2. The circuit according to claim 1 , further comprising a second circuit,
wherein the second circuit is electrically connected to the sixth node, and
wherein the second circuit is configured to input voltage higher than voltage of the sixth node to the gate of the second transistor.
3. The circuit according to claim 1 , further comprising a seventh node and an eighth node,
wherein the first circuit includes a fourth transistor and a second capacitor,
wherein a first terminal of the second capacitor is electrically connected to the gate of the first transistor,
wherein a second terminal of the second capacitor is electrically connected to the fifth node,
wherein the fourth transistor is configured to control electrical continuity between the seventh node and the gate of the first transistor, and
wherein a gate of the fourth transistor is electrically connected to the eighth node.
4. The circuit according to claim 2 , further comprising seventh to ninth nodes,
wherein the first circuit includes a fourth transistor and a second capacitor,
wherein the second circuit includes a fifth transistor and a third capacitor,
wherein a first terminal of the second capacitor is electrically connected to the gate of the first transistor,
wherein a second terminal of the second capacitor is electrically connected to the fifth node,
wherein the fourth transistor is configured to control electrical continuity between the seventh node and the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the eighth node,
wherein a first terminal of the third capacitor is electrically connected to the gate of the second transistor,
wherein a second terminal of the third capacitor is electrically connected to the sixth node,
wherein the fifth transistor is configured to control electrical continuity between the seventh node and the gate of the second transistor, and
wherein a gate of the fifth transistor is electrically connected to the ninth node.
5. The circuit according to claim 1 , wherein a channel formation region of each of the first transistor and the second transistor includes a metal oxide.
6. The circuit according to claim 1 , wherein a channel formation region of each of the first to third transistors includes a metal oxide.
7. The circuit according to claim 3 , wherein a channel formation region of the fourth transistor includes a metal oxide.
8. The circuit according to claim 4 , wherein a channel formation region of each of the fourth transistor and the fifth transistor includes a metal oxide.
9. A logic circuit comprising a backup circuit and a first logic circuit,
wherein the backup circuit includes the circuit according to claim 1 ,
wherein the first logic circuit includes an input node and an output node,
wherein the output node is electrically connected to the second node of the backup circuit, and
wherein the input node is electrically connected to the third node of the backup circuit.
10. The logic circuit according to claim 9 , wherein the backup circuit and the first logic circuit are stacked.
11. A processor comprising a plurality of scan flip-flops,
wherein the plurality of scan flip-flops each include a first input node, a second input node, a first output node, and a backup circuit,
wherein the backup circuit includes the circuit according to claim 1 , and
wherein in the plurality of scan flip-flops, the first output node is electrically connected to the second node of the backup circuit, and the second input node is electrically connected to the third node of the backup circuit.
12. An electronic component comprising a chip and a lead,
wherein the lead is electrically connected to the chip, and
wherein the chip includes the processor according to claim 11 .
13. An electronic device comprising:
a wireless communication device;
a sensor; and
the processor according to claim 11 .
14. An electronic device comprising:
the processor according to claim 11 ; and
at least one of a display device, a touch sensor, a microphone, a speaker, an operation key, and a housing.
15. A processor comprising:
a first scan flip-flop;
a second scan flip-flop;
a first combinational circuit; and
a second combinational circuit,
wherein the first scan flip-flop includes a first input node, a second input node, a first output node, and a first backup circuit,
wherein the second scan flip-flop includes a third input node, a fourth input node, a second output node, and a second backup circuit,
wherein the first backup circuit and the second backup circuit each include the circuit according to claim 1 ,
wherein an output node of the first combinational circuit is electrically connected to the first input node,
wherein an input node of the second combinational circuit is electrically connected to the first output node,
wherein an output node of the second combinational circuit is electrically connected to the third input node,
wherein the second node of the first backup circuit is electrically connected to the first output node,
wherein the third node of the first backup circuit is electrically connected to the second input node,
wherein the second node of the second backup circuit is electrically connected to the second output node,
wherein the third node of the second backup circuit is electrically connected to the fourth input node, and
wherein the fourth node of the second backup circuit is electrically connected to the first output node.
16. An electronic component comprising a chip and a lead,
wherein the lead is electrically connected to the chip, and
wherein the chip includes the processor according to claim 15 .
17. An electronic device comprising:
a wireless communication device;
a sensor; and
the processor according to claim 15 .
18. An electronic device comprising:
the processor according to claim 15 ; and
at least one of a display device, a touch sensor, a microphone, a speaker, an operation key, and a housing.