Resistance change memory device and fabrication method thereof
The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.
1. A fabrication method of a resistance change memory device, comprising:
forming starting layers on a substrate, wherein the starting layers comprise a dielectric layer;
forming a first resistance change memory stack in the dielectric layer for a first resistance change memory element, wherein the step of forming the first resistance change memory stack in the dielectric layer for the first resistance change memory element comprises:
etching an area in the dielectric layer;
depositing the first resistance change memory stack to the area; and
planarizing the dielectric layer; and
forming a second resistance change memory stack in the dielectric layer for a second resistance change memory element,
wherein an accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element,
wherein the first resistance change memory stack comprises a first phase change material, the second resistance change memory stack comprises a second phase change material, and the accessing frequency of the first phase change material is different from the accessing frequency of the second phase change material.
2. The fabrication method of the resistance change memory device according to claim 1 , wherein the accessing frequency of the first resistance change memory element is higher than the accessing frequency of the second resistance change memory element.
3. The fabrication method of the resistance change memory device according to claim 1 , wherein the first phase change material is different from the second phase change material.
4. The fabrication method of the resistance change memory device according to claim 3 , wherein a crystallization speed of the first phase change material is faster than a crystallization speed of the second phase change material.
5. The fabrication method of the resistance change memory device according to claim 3 , wherein the first phase change material is Ge-rich GeSbTe (GST) material, and the second phase change material is a SbTe-based material.
6. The fabrication method of the resistance change memory device according to claim 1 , wherein the first resistance change memory element and the second resistance change memory element are on the same chip.
7. The fabrication method of the resistance change memory device according to claim 1 , wherein the first resistance change memory stack comprises a first phase change material layer and a top electrode layer, and the step of depositing the first resistance change memory stack to the area comprises:
sequentially forming the first phase change material layer and the top electrode layer on the dielectric layer.
8. The fabrication method of the resistance change memory device according to claim 1 , wherein the step of forming the second resistance change memory stack in the dielectric layer for the second resistance change memory element comprises:
etching another area in the dielectric layer;
depositing the second resistance change memory stack to the another area; and
planarizing the dielectric layer.
9. The fabrication method of the resistance change memory device according to claim 8 , wherein the second resistance change memory stack comprises a second phase change material layer and a top electrode layer, and the step of depositing the second resistance change memory stack to the another area comprises:
sequentially forming the second phase change material layer and the top electrode layer on the dielectric layer.
10. The fabrication method of the resistance change memory device according to claim 1 , wherein the starting layers further comprise a word line layer, a bottom electrode layer, a switch layer, and a middle electrode layer, and the step of forming the starting layers on the substrate comprises:
sequentially forming the word line layer, the bottom electrode layer, the switch layer, the middle electrode layer, and the dielectric layer on the substrate.
11. The fabrication method of the resistance change memory device according to claim 10 , further comprising:
forming a wording pattern;
backfilling a dielectric material to a space between the wording pattern; and
planarizing the dielectric layer.
12. The fabrication method of the resistance change memory device according to claim 1 , further comprising:
forming bit line contacts on the substrate, wherein the bit line contacts pass through the starting layers; and
forming a bit line pattern on the dielectric layer, wherein the bit line pattern contacts the bit line contacts.