CMOS inverter circuit that suppresses leakage currents

1. An inverter circuit, comprising:

a first P-channel metal insulator semiconductor field effect transistor (MISFET) having a source connected to a positive-side terminal and a drain connected to an output terminal;

a first N-channel MISFET having a source connected to a negative-side terminal and a drain connected to the output terminal, the negative-side terminal having a potential lower than that of the positive-side terminal;

a first delay element connected between a gate of the first P-channel MISFET and an input terminal to which an input signal is supplied;

a first switch element connected in parallel with the first delay element between the input terminal and the gate of the first P-channel MISFET;

a second delay element connected between the input terminal and a gate of the first N-channel MISFET,

a second switch element connected in parallel with the second delay element between the input terminal and the gate of the first N-channel MISFET,

wherein the first switch element comprises a first transfer gate having an inverting gate input and the second switch element comprises a second transfer gate having a non-inverting gate input;

an inverter connected between the output terminal and each of the inverting gate input and the non-inverting gate input; and

wherein the first and second switch elements operate in response to a potential on the output terminal.

2. The inverter circuit according to claim 1 , wherein the first switch element is turned off when the output terminal is set to a first potential and turned on when the output terminal is set to a second potential higher than the first potential, and

wherein the second switch element is turned on when the output terminal is set to the first potential, and turned off when the output terminal is set to the second potential.

3. The inverter circuit according to claim 1 , wherein the first switch element includes a second N-channel MISFET associated with the first transfer gate,

wherein the second switch element includes a second P-channel MISFET associated with the second transfer gate,

wherein one of a source and a drain of the second N-channel MISFET is connected to the input terminal and the other of the source and the drain is connected to the gate of the first P-channel MISFET,

wherein one of a source and a drain of the second P-channel MISFET is connected to the input terminal and the other of the source and the drain is connected to the gate of the first N-channel MISFET, and

wherein gates of the second N-channel MISFET and the second P-channel MISFET are connected to the output terminal.

4. The inverter circuit according to claim 3 ,

wherein the first switch element further includes a third P-channel MISFET associated with the first transfer gate, one of a source and drain of the third P-channel MISFET being connected to the input terminal and the other being connected to the gate of the first P-channel MISFET,

wherein the second switch element further includes a third N-channel MISFET associated with the second transfer gate, one of a source and drain of the third N-channel MISFET being connected to the input terminal and the other being connected to the gate of the first N-channel MISFET,

wherein the inverter has an output connected to gates of the third P-channel MISFET and the third N-channel MISFET.

5. The inverter circuit according to claim 1 , wherein each of the first and second delay elements includes a resistor element.

6. The inverter circuit according to claim 5 , wherein resistance values of the respective resistor elements are selected according to the following:

0.8

≤

R

R

⁢

⁢

1

·

C

GP

⁢

⁢

11

R

R

⁢

⁢

2

·

C

GN

⁢

⁢

11

≤

1.2

,

where R R1 represents a resistance of the first delay element, R R2 represents a resistance of the second delay element, C GP11 represents a gate capacitance of the first P-channel MISFET, and C GN11 represents a gate capacitance of the first N-channel MISFET.

7. The inverter circuit according to claim 6 , wherein the resistance values of the respective resistor elements are selected according to the following:

0.9

≤

R

R

⁢

⁢

1

·

C

GP

⁢

⁢

11

R

R

⁢

⁢

2

·

C

GN

⁢

⁢

11

≤

1.1

.

8. The inverter circuit according to claim 1 , wherein each transfer gate respectively comprises:

a second P-channel MISFET having a gate connected with a first fixed potential; and

a second N-channel MISFET having a gate connected with a second fixed potential,

wherein the second P-channel MISFET and the second N-channel MISFET have commonly-connected sources and commonly-connected drains.

9. The inverter circuit according to claim 8 , wherein the first fixed potential comprises a circuit-ground level, and wherein the second fixed potential comprises a power supply level.

10. An inverter circuit, comprising:

a first P-channel metal insulator semiconductor field effect transistor (MISFET) having a source connected to a positive-side terminal and a drain connected to an output terminal;

a first N-channel MISFET having a source connected to a negative-side terminal and a drain connected to the output terminal, the negative-side terminal having a potential lower than that of the positive-side terminal;

a first resistor element connected between an input terminal to which an input signal is supplied and a gate of the first P-channel MISFET;

a second resistor element connected between the input terminal and a gate of the first N-channel MISFET;

a first transfer gate having an inverting gate input and comprising a second N-channel MISFET connected in parallel with the first resistor element;

a second transfer gate having a non-inverting gate input and comprising a second P-channel MISFET connected in parallel with the second resistor element,

wherein one of a source and drain of the second N-channel MISFET is connected to the input terminal and the other is connected to the gate of the first P-channel MISFET,

wherein one of a source and drain of the second P-channel MISFET is connected to the input terminal and the other is connected to the gate of the first N-channel MISFET, and

wherein the gates of the second N-channel MISFET and the second P-channel MISFET are connected to the output terminal; and

an inverter connected between the output terminal and each of the inverting gate input and the non-inverting gate input.

11. A semiconductor integrated circuit, comprising:

a level shifter configured to generate an output signal through level shifting of an input signal,

wherein the level shifter includes:

an output stage configured to output an output signal from an output terminal,

wherein the output stage includes an inverter circuit comprising:

a first P-channel metal insulator semiconductor field effect transistor (MISFET) having a source connected to a positive-side terminal and a drain connected to the output terminal;

a first N-channel MISFET having a source connected to a negative-side terminal and a drain connected to the output terminal, the negative-side terminal having a potential lower than that of the positive-side terminal;

a first delay element connected between a gate of the first P-channel MISFET and an input terminal to which an input signal is supplied;

a first switch element connected in parallel with the first delay element between the input terminal and the gate of the first P-channel MISFET;

a second delay element connected between the input terminal and a gate of the first N-channel MISFET;

a second switch element connected in parallel with the second delay element between the input terminal and the gate of the first N-channel MISFET,

wherein each of the first and second delay-switch elements includes a respective transfer gate, wherein each transfer gate comprises a gate input, and

wherein the first and second switch elements operate in response to a potential on the output terminal; and

an inverter connected between the output terminal and the gate input of each transfer gate.

12. The semiconductor integrated circuit according to claim 11 , further comprising:

a capacitor configured for a boosting operation in a charge pump circuit;

a MOS transistor configured to switch a connection of the capacitor in the charge pump circuit; and

a second level shifter configured to generate a second output signal through level shifting of a control signal, and to supply the second output signal from a second output terminal to a gate of the MOS transistor,

wherein the second level shifter includes:

a second output stage configured to output the second output signal from the second output terminal,

wherein the second output stage includes a second inverter circuit comprising:

a second P-channel MISFET having a source connected to a positive-side terminal and a drain connected to the second output terminal;

a second N-channel MISFET having a source connected to a negative-side terminal and a drain connected to the output terminal, the negative-side terminal having a potential lower than that of the positive-side terminal;

a third delay element connected between a gate of the second P-channel MISFET and a second input terminal to which a second input signal is supplied;

a third switch element connected in parallel with the third delay element between the second input terminal and the gate of the second P-channel MISFET;

a fourth delay element connected between the second input terminal and a gate of the second N-channel MISFET; and

a fourth switch element connected in parallel with the fourth delay element between the second input terminal and the gate of the second N-channel MISFET,

wherein the third and fourth switch elements operate in response to a potential on the second output terminal.

13. The semiconductor integrated circuit according to claim 11 , wherein the first switch element is turned off when the output terminal is set to a first potential and turned on when the output terminal is set to a second potential higher than the first potential, and

wherein the second switch element is turned on when the output terminal is set to the first potential, and turned off when the output terminal is set to the second potential.

14. The semiconductor integrated circuit according to claim 11 , wherein the first switch element includes a second N-channel MISFET associated with the transfer gate of the first switch element,

wherein the second switch element includes a second P-channel MISFET associated with the transfer gate of the second switch element,

wherein one of a source and a drain of the second N-channel MISFET is connected to the input terminal and the other of the source and the drain is connected to the gate of the first P-channel MISFET,

wherein one of a source and a drain of the second P-channel MISFET is connected to the input terminal and the other of the source and the drain is connected to the gate of the first N-channel MISFET, and

wherein gates of the second N-channel MISFET and the second P-channel MISFET are connected to the output terminal.

15. The semiconductor integrated circuit according to claim 14 ,

wherein the first switch element further includes a third P-channel MISFET associated with the transfer gate of the first switch element, one of a source and drain of the third P-channel MISFET being connected to the input terminal and the other being connected to the gate of the first P-channel MISFET,

wherein the second switch element further includes a third N-channel MISFET associated with the transfer gate of the second switch element, one of a source and drain of the third N-channel MISFET being connected to the input terminal and the other being connected to the gate of the first N-channel MISFET,

wherein the inverter has an output connected to gates of the third P-channel MISFET and the third N-channel MISFET.

16. The semiconductor integrated circuit according to claim 11 , wherein each of the first and second delay elements includes a resistor element.

17. The semiconductor integrated circuit according to claim 16 , wherein resistance values of the respective resistor elements are selected according to the following:

0.8

≤

R

R

⁢

⁢

1

·

C

GP

⁢

⁢

11

R

R

⁢

⁢

2

·

C

GN

⁢

⁢

11

≤

1.2

,

where R R1 represents a resistance of the first delay element, R R2 represents a resistance of the second delay element, C GP11 represents a gate capacitance of the first P-channel MISFET, and C GN11 represents a gate capacitance of the first N-channel MISFET.

18. The semiconductor integrated circuit according to claim 17 , wherein the resistance values of the respective resistor elements are selected according to the following:

0.9

≤

R

R

⁢

⁢

1

·

C

GP

⁢

⁢

11

R

R

⁢

⁢

2

·

C

GN

⁢

⁢

11

≤

1.1

.

19. The semiconductor integrated circuit according to claim 11 , wherein each of the first and second delay elements includes a respective transfer gate, wherein each transfer gate respectively comprises:

a second P-channel MISFET having a gate connected with a first fixed potential; and

a second N-channel MISFET having a gate connected with a second fixed potential,

wherein the second P-channel MISFET and the second N-channel MISFET have commonly-connected sources and commonly-connected drains.

20. The semiconductor integrated circuit according to claim 19 , wherein the first fixed potential comprises a circuit-ground level, and wherein the second fixed potential comprises a power supply level.