Method and system for computer-aided design of radiation-hardened integrated circuits
A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.
1. A computer-implemented method for designing a radiation-hardened integrated circuit comprising the steps of:
entering a schematic of a circuit, said circuit comprising at least a portion of an integrated circuit, and a list of requirements comprising a radiation-hardness requirement and another goal, said radiation-hardness requirement comprising a requirement that the circuit meet a predetermined specification upon exposure to ionizing radiation at a specified first Total Ionizing Dose (TID) level;
generating an initial layout of the circuit;
assessing, using a computing system, a rad-hard performance of the circuit, said rad-hard performance characterized by a second TID level, upon exposure to which the circuit, if fabricated as laid out, will fail to meet the predetermined specification;
evaluating a trade-off between the radiation-hardness requirement and the other goal;
suggesting a change to the layout if the second TID level determined in assessing the rad-hard performance does not meet or exceed the first TID level specified in the radiation-hardness requirement; and
changing the layout in response to the suggested change, whereby a resulting design for the circuit is produced that, if fabricated, will meet an overall IC design goal that achieves a predetermined rad-hard performance in conjunction with an IC design specification related to the other goal.
2. The computer-implemented method of claim 1 , wherein the other goal is characterized by a radiation-insensitive parameter.
3. The computer-implemented method of claim 1 , wherein the step of changing the layout is performed by the computing system.
4. The computer-implemented method of claim 2 , wherein said radiation-insensitive parameter comprises a die area of the circuit.
5. The computer-implemented method of claim 1 , wherein said other goal is characterized by a parameter that changes as a function of total ionizing dose.
6. The computer-implemented method of claim 1 , wherein said other goal is characterized by a parameter that changes in response to the suggested change to the layout.
7. The computer-implemented method of claim 1 , wherein the step of entering a schematic further comprises providing a schematic of an existing circuit that is known not to meet said radiation-hardness requirement, and the step of generating an initial layout further comprises providing a layout of said existing circuit.
8. The computer-implemented method of claim 1 , wherein the circuit comprises a cell, and the resulting design for the circuit that, if fabricated, will meet the radiation-hardness requirement is included in a cell library that can be used as a component of a process design kit.
9. The computer-implemented method of claim 1 , wherein the step of suggesting a change to the layout is performed by the computing system.
10. The computer-implemented method of claim 9 , wherein the step of suggesting a change to the layout further comprises displaying the suggested change in a physical design layout view.