High-speed data connector
View Patent ↗A transceiver connector may include a bottomside connector. The bottomside connector may include a first ground pin adjacent to an edge of the bottomside connector, a first high-speed differential input pin adjacent to the first ground pin, a second high-speed differential input pin adjacent to the first high-speed differential input pin, a second ground pin adjacent to the second high-speed differential input pin, a serial interface data line pin adjacent to the second ground pin, a serial interface clock pin adjacent to the serial interface data line pin, a third ground pin adjacent to the serial interface clock pin, a first high-speed differential output pin adjacent to the third ground pin, a second high-speed differential output pin adjacent to the first high-speed differential output pin, and a fourth ground pin adjacent to the second high-speed differential output pin.
1. A transceiver connector comprising:
a bottomside connector including:
a first ground pin adjacent to an edge of the bottomside connector;
a first high-speed differential input pin adjacent to the first ground pin;
a second high-speed differential input pin adjacent to the first high-speed differential input pin;
a second ground pin adjacent to the second high-speed differential input pin;
a serial interface data line pin adjacent to the second ground pin;
a serial interface clock pin adjacent to the serial interface data line pin;
a third ground pin adjacent to the serial interface clock pin;
a first high-speed differential output pin adjacent to the third ground pin;
a second high-speed differential output pin adjacent to the first high-speed differential output pin; and
a fourth ground pin adjacent to the second high-speed differential output pin.
2. The transceiver connector of claim 1 , further comprising a topside connector including:
a low-speed interface pin adjacent to an edge of the topside connector;
a fifth ground pin adjacent to the low-speed interface pin;
a third high-speed differential output pin adjacent to the fifth ground pin;
a fourth high-speed differential output pin adjacent to the third high-speed differential output pin;
a sixth ground pin adjacent to the fourth high-speed differential output pin;
a receiver power pin adjacent to the sixth ground pin;
a transmitter power pin adjacent to the receiver power pin;
a seventh ground pin adjacent to the transmitter power pin;
a third high-speed differential input pin adjacent to the seventh ground pin;
a fourth high-speed differential input pin adjacent to the third high-speed differential input pin; and
an eighth ground pin adjacent to the fourth high-speed differential input pin.
3. The transceiver connector of claim 2 , wherein the low-speed interface pin comprises an interface for signaling that there is a fault in a transceiver associated with the transceiver connector.
4. The transceiver connector of claim 2 , wherein the low-speed interface pin has a width narrower than a width of the fifth ground pin.
5. The transceiver connector of claim 1 , wherein the serial interface data line pin and the serial interface clock pin comprises a 2-wire serial interface for communicating transmitter disable signals.
6. The transceiver connector of claim 1 , wherein the serial interface data line pin and the serial interface clock pin comprises a 2-wire serial interface for communicating loss of signal signals.
7. A transceiver connector comprising:
a bottomside connector including:
a first ground pin adjacent to an edge of the bottomside connector;
a first high-speed differential input pin adjacent to the first ground pin;
a second high-speed differential input pin adjacent to the first high-speed differential input pin;
a second ground pin adjacent to the second high-speed differential input pin;
a serial interface data line pin adjacent to the second ground pin;
a serial interface clock pin adjacent to the serial interface data line pin;
a transceiver module detection pin adjacent to the serial interface clock pin;
a third ground pin adjacent to the transceiver module detection pin;
a first high-speed differential output pin adjacent to the third ground pin;
a second high-speed differential output pin adjacent to the first high-speed differential output pin; and
a fourth ground pin adjacent to the second high-speed differential output pin.
8. The transceiver connector of claim 7 , further comprising a topside connector including:
a low-speed interface pin adjacent to an edge of the topside connector;
a fifth ground pin adjacent to the low-speed interface pin;
a third high-speed differential output pin adjacent to the fifth ground pin;
a fourth high-speed differential output pin adjacent to the third high-speed differential output pin;
a sixth ground pin adjacent to the fourth high-speed differential output pin;
a receiver power pin adjacent to the sixth ground pin;
a transmitter power pin adjacent to the receiver power pin;
a seventh ground pin adjacent to the transmitter power pin;
a third high-speed differential input pin adjacent to the seventh ground pin;
a fourth high-speed differential input pin adjacent to the third high-speed differential input pin; and
an eighth ground pin adjacent to the fourth high-speed differential input pin.
9. The transceiver connector of claim 8 , wherein the low-speed interface pin comprises an interface for signaling that there is a fault in a transceiver associated with the transceiver connector.
10. The transceiver connector of claim 8 , wherein the low-speed interface pin has a width narrower than a width of the fifth ground pin.
11. The transceiver connector of claim 7 , wherein the serial interface data line pin and the serial interface clock pin comprises a 2-wire serial interface for communicating transmitter disable signals.
12. The transceiver connector of claim 7 , wherein the serial interface data line pin and the serial interface clock pin comprises a 2-wire serial interface for communicating loss of signal signals.
13. The transceiver connector of claim 7 , wherein the first ground pin has a width narrower than a width of the first high-speed differential input pin.
14. A transceiver connector comprising:
a topside connector including:
a low-speed interface pin adjacent to an edge of the topside connector;
a first ground pin adjacent to the low-speed interface pin;
a first high-speed differential output pin adjacent to the first ground pin;
a second high-speed differential output pin adjacent to the first high-speed differential output pin;
a second ground pin adjacent to the second high-speed differential output pin;
a receiver power pin adjacent to the second ground pin;
a transmitter power pin adjacent to the receiver power pin;
a third ground pin adjacent to the transmitter power pin;
a first high-speed differential input pin adjacent to the third ground pin;
a second high-speed differential input pin adjacent to the first high-speed differential input pin; and
a fourth ground pin adjacent to the second high-speed differential input pin.
15. The transceiver connector of claim 14 , wherein the low-speed interface pin comprises an interface for signaling that there is a fault in a transceiver associated with the transceiver connector.
16. The transceiver connector of claim 15 , further comprising a bottomside connector including:
a fifth ground pin adjacent to an edge of the bottomside connector;
a third high-speed differential input pin adjacent to the fifth ground pin;
a fourth high-speed differential input pin adjacent to the third high-speed differential input pin;
a sixth ground pin adjacent to the fourth high-speed differential input pin;
a serial interface data line pin adjacent to the sixth ground pin;
a serial interface clock pin adjacent to the serial interface data line pin;
a seventh ground pin adjacent to the serial interface clock pin;
a third high-speed differential output pin adjacent to the seventh ground pin;
a fourth high-speed differential output pin adjacent to the third high-speed differential output pin; and
an eighth ground pin adjacent to the fourth high-speed differential output pin.
17. The transceiver connector of claim 16 , wherein the low-speed interface pin and the fifth ground pin each have a width narrower than a width of the first ground pin.
18. The transceiver of claim 17 , wherein the serial interface data line pin and the serial interface clock pin comprises a 2-wire serial interface for communicating transmitter disable signals and loss of signal signals.
19. The transceiver connector of claim 15 , further comprising a bottomside connector including:
a fifth ground pin adjacent to an edge of the bottomside connector;
a third high-speed differential input pin adjacent to the fifth ground pin;
a fourth high-speed differential input pin adjacent to the third high-speed differential input pin;
a sixth ground pin adjacent to the fourth high-speed differential input pin;
a serial interface data line pin adjacent to the sixth ground pin;
a serial interface clock pin adjacent to the serial interface data line pin;
a transceiver module detection pin adjacent to the serial interface clock pin;
a seventh ground pin adjacent to the transceiver module detection pin;
a third high-speed differential output pin adjacent to the seventh ground pin;
a fourth high-speed differential output pin adjacent to the third high-speed differential output pin; and
an eighth ground pin adjacent to the fourth high-speed differential output pin.
20. The transceiver connector of claim 19 , wherein the low-speed interface pin and the fifth ground pin each have a width narrower than a width of the first ground pin.