Non-volatile SRAM with multiple storage states
Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include a pair of programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.
1. A multi-storage state non-volatile random access memory device, comprising:
a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell each comprises:
a first transistor having a first terminal coupled to a first node, a second terminal coupled to a first programmable resistive device, and a control terminal coupled to a sense enable line;
a second transistor having a first terminal coupled to a second node, a second terminal coupled to a second programmable resistive device, and a control terminal coupled to the sense enable line;
the first programmable resistive device, which is coupled between a first bit line and the second terminal of the first transistors; and
the second programmable resistive device, which is coupled between a second bit line and the second terminal of the second transistor; and
a first word line transistor and a second word line transistor that form a write port, wherein the first word line transistor is coupled to the first bit line, wherein the second word line transistor is coupled to the second bit line, and wherein the first and second word line transistors are configured to be activated to enable a write or a read of a logic state of the multi-storage state non-volatile random access memory device.
2. The multi-storage state non-volatile random access memory device of claim 1 , wherein the first programmable resistive device and the second programmable resistive device are configured to be programmed to different resistive states corresponding to the logic state of the multi-storage state non-volatile random access memory device, in response to a write operation of the multi-storage state non-volatile random access memory device.
3. The multi-storage state non-volatile random access memory device of claim 1 , wherein the first programmable resistive device and the second programmable resistive device are selected from at least one of a magnetic tunnel junction resistor, a conductive-bridge resistor, a metal-oxide bipolar filament resistor, a metal-oxide bipolar interface effect resistor, and an amorphous silicon switching medium resistor.
4. The multi-storage state non-volatile random access memory device of claim 1 , wherein a resistive state of the first programmable resistive device and a resistive state of the second programmable resistive device are dynamically configurable, in response to a direction of current flow through the first programmable resistive device and the second programmable resistive device.
5. The multi-storage state non-volatile random access memory device of claim 1 , wherein the logic state corresponds to a relative resistance value between the first programmable resistive device and the second programmable resistive device.
6. The multi-storage state non-volatile random access memory device of claim 1 , further comprising:
a bistable latch coupled to the first node and the second node, wherein the bistable latch is formed from a first inversion circuit and a second inversion circuit, wherein an output terminal of the first inversion circuit is coupled to an input terminal of the second inversion circuit, and wherein an output terminal of the second inversion circuit is coupled to an input terminal of the first inversion circuit.
7. The multi-storage state non-volatile random access memory device of claim 1 , wherein the multi-storage non-volatile random access memory device comprises a static non-volatile random access memory device.
8. A multi-storage state non-volatile random access memory device, comprising:
a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell each comprises:
a first transistor having a first terminal coupled to a first node, a second terminal coupled to a first programmable resistive device, and a control terminal coupled to a sense enable line;
a second transistor having a first terminal coupled to a second node, a second terminal coupled to a second programmable resistive device, and a control terminal coupled to the sense enable line;
the first programmable resistive device, which is coupled between a third node and the second terminal of the first transistor; and
the second programmable resistive device, which is coupled between the third node and the second terminal of the second transistor;
a first word line transistor and a second word line transistor that form a write port, wherein the first word line transistor is coupled to a first bit line, wherein the second word line transistor is coupled to a second bit line, and wherein the first and second word line transistors are configured to be activated to enable a write or a read of a logic state of the multi-storage state non-volatile random access memory device.
9. The multi-storage state non-volatile random access memory device of claim 8 , further comprising an enable transistor coupled between the third node and a supply line.
10. The multi-storage state non-volatile random access memory device of claim 8 , further comprising:
a bistable latch coupled to the first node and the second node, wherein the bistable latch is formed from a first inversion circuit and a second inversion circuit, wherein an output terminal of the first inversion circuit is coupled to an input terminal of the second inversion circuit, and wherein an output terminal of the second inversion circuit is coupled to an input terminal of the first inversion circuit.
11. The multi-storage state non-volatile random access memory device of claim 8 , wherein the first programmable resistive device and the second programmable resistive device are selected from at least one of a magnetic tunnel junction resistor, a conductive-bridge resistor, a metal-oxide bipolar filament resistor, a metal-oxide bipolar interface effect resistor, and an amorphous silicon switching medium resistor.
12. The multi-storage state non-volatile random access memory device of claim 8 , wherein the multi-storage non-volatile random access memory device comprises a static non-volatile random access memory device.