Clock selection circuit and power supply device equipped with the same
View Patent ↗To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.
1. A clock selection circuit comprising:
a clock detection circuit which detects a first clock to output a detected signal;
a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level; and
a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level,
wherein the output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.
2. The clock selection circuit according to claim 1 , wherein the clock detection circuit has a first D flip-flop circuit having a set terminal to which the first clock is inputted, and a second D flip-flop circuit having an input terminal to which an output of the first D flip-flop circuit is inputted,
wherein the second clock is inputted to respective clock terminals of the first and second D flip-flop circuits, and
wherein an output of the second D flip-flop circuit is the detected signal.
3. The clock selection circuit according to claim 1 , further including an internal oscillation circuit which generates an internal clock,
wherein the first clock is a clock supplied from the outside of the clock selection circuit, and
wherein the second clock is the internal clock.
4. The clock selection circuit according to claim 2 , further including an internal oscillation circuit which generates an internal clock,
wherein the first clock is a clock supplied from the outside of the clock selection circuit, and
wherein the second clock is the internal clock.
5. A power supply device comprising:
a clock selection circuit according to claim 1 .
6. A power supply device comprising:
a clock selection circuit according to claim 2 .
7. A power supply device comprising:
a clock selection circuit according to claim 3 .
8. A power supply device comprising:
a clock selection circuit according to claim 4 .