Compact class-F chip and wire matching topology

1. An amplifier circuit, comprising:

an RF input port;

an RF output port;

a reference potential port;

an RF amplifier having an input terminal and a first output terminal, the RF amplifier being configured to amplify an RF signal across an RF frequency range;

an output impedance matching network electrically coupling the first output terminal to the RF output port, wherein the output impedance matching network comprises:

a first inductor electrically connected in series between the first output terminal and the RF output port;

a first LC resonator directly electrically connected between the first output terminal and the reference potential port;

a second LC resonator directly electrically connected between the first output terminal and the reference potential port and being in parallel with the first LC resonator;

wherein the first LC resonator is configured to compensate for an output capacitance of the RF amplifier at a center frequency of the RF signal, and

wherein the second LC resonator is configured to compensate for a second order harmonic of the RF signal.

2. The amplifier circuit of claim 1 , wherein the first LC resonator is configured to negate an output capacitance of the RF amplifier at the center frequency, and wherein the second LC resonator is configured to present a short circuit at the second order harmonic of the RF signal.

3. The amplifier circuit of claim 2 , wherein the first inductor is configured to present a high impedance at a third order harmonic of the center frequency.

4. The amplifier circuit of claim 3 , wherein the first LC resonator comprises a second inductor and a first capacitor, wherein the second LC resonator comprises a third inductor and a second capacitor, wherein the second inductor is directly electrically connected to the first output terminal and the first capacitor, wherein the first capacitor is directly electrically connected to the second inductor and the reference potential port, wherein the third inductor is directly electrically connected to the first output terminal and the second capacitor, wherein the second capacitor is directly electrically connected to the third inductor and the reference potential port, and wherein the first inductor is directly electrically connected to the first output terminal.

5. The amplifier circuit of claim 4 , wherein the second and third inductors are arranged in a mutually inductive configuration.

6. The amplifier circuit of claim 4 , further comprising:

a third capacitor electrically connected between a node that connects the first capacitor to the second inductor and the reference potential port,

wherein the third capacitor is configured to present a short circuit at very low frequency values that are below the RF frequency range.

7. The amplifier circuit of claim 4 , further comprising:

a fourth capacitor electrically connected in series between the first inductor and the RF output port,

wherein the fourth capacitor and the third inductor are collectively configured to present a short circuit at the center frequency.

8. The amplifier circuit of claim 1 , further comprising:

an input impedance matching network electrically coupling the RF input port to the input terminal, wherein the input impedance matching network comprises:

a fourth inductor electrically connected in series between the RF input port and the first input terminal;

a third LC resonator directly electrically connected between the first input terminal and the reference potential port;

a fourth LC resonator directly electrically connected between the first input terminal and the reference potential port and being in parallel with the third LC resonator

wherein the third LC resonator is configured to compensate for an input capacitance of the RF amplifier at the center frequency, and

wherein the fourth LC resonator is configured to compensate for a second order harmonic of the RF signal.

9. The amplifier circuit of claim 8 , wherein the third LC resonator is configured to negate an input capacitance of the RF amplifier at the center frequency, wherein the fourth LC resonator is configured to present a short circuit at the second order harmonic, and wherein the fourth inductor is configured to present a high impedance at a third order harmonic of the center frequency.

10. An amplifier circuit, comprising:

an RF input port;

an RF output port;

a reference potential port;

an RF amplifier having an input terminal and a first output terminal, the RF amplifier being configured to amplify an RF signal across an RF frequency range;

an input impedance matching network electrically coupling the RF input port to the input terminal, wherein the input impedance matching network comprises:

a fourth inductor electrically connected in series between the RF input port and the first input terminal;

a third LC resonator directly electrically connected between the first input terminal and the reference potential port;

a fourth LC resonator directly electrically connected between the first input terminal and the reference potential port and being in parallel with the third LC resonator

wherein the third LC resonator is configured to compensate for an input capacitance of the RF amplifier at a center frequency of the RF signal, and

wherein the fourth LC resonator is configured to compensate for a second order harmonic of the RF signal.

11. The amplifier circuit of claim 10 , wherein the third LC resonator is configured to negate an input capacitance of the RF amplifier at the center frequency, wherein the fourth LC resonator is configured to present a short circuit at the second order harmonic, and wherein the fourth inductor is configured to present a high impedance at a third order harmonic of the center frequency.

12. A packaged amplifier circuit, comprising:

an RF input lead;

an RF output lead;

a substrate with an electrically conductive source pad, the source pad being connected to a reference potential lead;

an RF transistor having gate, source and drain terminals, the RF transistor being configured to amplify an RF signal across an RF frequency range, the RF transistor being mounted on the substrate with the source terminal directly facing and electrically connected to the source pad;

an input impedance matching network electrically coupling the RF input lead to the gate terminal;

an output impedance matching network electrically coupling the drain terminal to the RF output lead;

wherein the output impedance matching network comprises:

first and second LC resonators each being connected in parallel with the source and drain terminals; and

a first inductor connected in series between the drain terminal and the RF output lead,

wherein the first LC resonator is configured to compensate for an output capacitance of the RF amplifier at a center frequency of the RF signal, and

wherein the second LC resonator is configured to compensate for a second order harmonic of the RF signal.

13. The amplifier circuit of claim 12 , wherein the first LC resonator is configured to negate a drain-source capacitance of the RF transistor at the center frequency, and wherein the second LC resonator is configured to present a short circuit the second order harmonic.

14. The amplifier circuit of claim 13 , wherein the first inductor is configured to present a high impedance at a third order harmonic of the center frequency.

15. The amplifier circuit of claim 14 , wherein the first LC resonator comprises a second inductor and a first capacitor, wherein the second LC resonator comprises a third inductor and a second capacitor, wherein the second inductor is directly electrically connected to the first output terminal and the first capacitor, wherein the first capacitor is directly electrically connected to the second inductor and the source pad, wherein the third inductor is directly electrically connected to the first output terminal and the second capacitor, wherein the second capacitor is directly electrically connected to the third inductor and the source pad, and wherein the first inductor is directly electrically connected to the first output terminal.

16. The amplifier circuit of claim 15 , wherein the first, second and third inductors are each formed by one or more electrically conductive bond wires, wherein the first and second capacitors are provided, respectively, by first and second chip capacitors, the first chip capacitor being mounted on the substrate with a lower terminal directly facing and electrically connected to the source pad and an upper terminal electrically connected to the bond wires of the second inductor, the second chip capacitor being mounted on the substrate with a first terminal directly facing and electrically connected to the source pad and an upper terminal electrically connected to the bond wires of the third inductor.

17. The amplifier circuit of claim 16 , wherein the bond wires of the second and third inductors are interdigitated with one another to provide a mutually inductive relationship between the second and third inductors.

18. The amplifier circuit of claim 16 , further comprising:

a third capacitor mounted on the substrate with a lower terminal facing and directly connected to the source pad and an upper terminal directly electrically connected to a node connecting the second inductor to the first capacitor,

wherein the third capacitor is configured to present a short circuit at very low frequency values that are below the RF frequency range.

19. The amplifier circuit of claim 16 , further comprising:

a fourth capacitor mounted on the substrate and connected in series between the first inductor and the RF output port,

wherein the fourth capacitor and the third inductor are collectively configured to present a short circuit at the center frequency.

20. The amplifier circuit of claim 12 , further comprising:

an input impedance matching network electrically coupling the RF input port to the input terminal, wherein the input impedance matching network comprises:

a fourth inductor electrically connected in series between the RF input port and the first input terminal;

a third LC resonator directly electrically connected between the first input terminal and the reference potential port;

a fourth LC resonator directly electrically connected between the first input terminal and the reference potential port and being in parallel with the third LC resonator

wherein the third LC resonator is configured to compensate for an input capacitance of the RF amplifier, and

wherein the fourth LC resonator is configured to compensate for a second order harmonic of the RF signal.