Fabric management system and method
A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. A primary master central processing system is configured to couple the plurality of PCIe subfabrics. A secondary master central processing system is configured to couple the plurality of PCIe subfabrics.
1. A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
a plurality of PCIe subfabrics, wherein each of the plurality of PCIe subfabrics includes:
a managing central processing unit, and
a PCIe fabric switch;
a primary master central processing system configured to couple the plurality of PCIe subfabrics and configured to:
send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics; and
a secondary master central processing system configured to couple the plurality of PCIe subfabrics and configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics in the event that the primary master central processing system fails;
wherein the primary master central processing system is configured to determine the topology of the plurality of PCIe subfabrics and determining the topology includes:
determining the number of managing central processing units included within the PCIe fabric,
determining the types of elements coupled with the PCIe fabric, and
providing topological information to the secondary master central processing system.
2. The PCIe fabric of claim 1 wherein the primary master central processing system includes:
a primary master central processing unit; and
a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics.
3. The PCIe fabric of claim 1 wherein the secondary master central processing system includes:
a secondary master central processing unit; and
a secondary fan-out switch configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics.
4. The PCIe fabric of claim 1 further comprising:
one or more communication paths configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.
5. The PCIe fabric of claim 1 wherein the plurality of elements include components of a data storage system.
6. The PCIe fabric of claim 1 wherein the plurality of elements includes one or more host elements.
7. The PCIe fabric of claim 6 wherein the one or more host elements include one or more compute modules.
8. The PCIe fabric of claim 1 wherein the plurality of elements includes one or more endpoint elements.
9. The PCIe fabric of claim 8 wherein the one or more endpoint elements include one or more of:
one or more host bus adaptors;
Serial Attached Small Computer System Interface (SAS) controllers;
SAS hard disk drives;
fiber channel adapters;
Ethernet adapters;
PCIe flash memory devices;
one or more InfiniBand (IB) adapters;
one or more Redundant Array of Independent Disks (RAID) adapters;
one or more network adapters; and
one or more general purpose graphics processing units.
10. A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
a plurality of PCIe subfabrics, wherein each of the plurality of PCIe subfabrics includes:
a managing central processing unit, and
a PCIe fabric switch;
a primary master central processing system configured to couple the plurality of PCIe subfabrics and including a primary master central processing unit and a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics, wherein the primary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics; and
a secondary master central processing system configured to couple the plurality of PCIe subfabrics configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics, wherein the secondary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics in the event that the primary master central processing system fails;
wherein the primary master central processing system is configured to determine the topology of the plurality of PCIe subfabrics and determining the topology includes:
determining the number of managing central processing units included within the PCIe fabric,
determining the types of elements coupled with the PCIe fabric, and
providing topological information to the secondary master central processing system.
11. The PCIe fabric of claim 10 further comprising:
one or more communication paths configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.
12. A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
a plurality of PCIe subfabrics, wherein each of the plurality of PCIe subfabrics includes a managing central processing unit and a PCIe fabric switch;
a primary master central processing system configured to couple the plurality of PCIe subfabrics and including a primary master central processing unit and a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics, wherein the primary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics; and
a secondary master central processing system configured to couple the plurality of PCIe subfabrics and including a secondary master central processing unit and a secondary fan-out switch configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics, wherein the secondary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics in the event that the primary master central processing system fails;
wherein the primary master central processing system is configured to determine the topology of the plurality of PCIe subfabrics and determining the topology of the plurality of PCIe subfabrics includes:
determining the number of managing central processing units included within the PCIe fabric,
determining the types of elements coupled with the PCIe fabric, and
providing topological information to the secondary master central processing system.