Leveling composition and method for electrodeposition of metals in microelectronics

1. A method of electroplating comprising:

providing a substrate and an electrolytic plating composition;

contacting the substrate with the electrolytic plating composition; and

applying an electrical current to the electrolytic plating composition to deposit a metal layer onto the substrate;

wherein the metal layer has a predetermined topography, and

wherein the electrolytic plating composition includes a source of metal ions and a compound of formula (I):

wherein X is Cl − , or Br − ;

R 1 is O, S or N;

R 2 , R 3 and R 4 are independently selected from the group consisting of hydrogen, unsubstituted or substituted alkyl, unsubstituted or substituted alkenyl, unsubstituted or substituted alkynyl, unsubstituted or substituted C 3-12 cycloalkyl, unsubstituted or substituted C 6-12 aryl, unsubstituted or substituted 3-12 membered heterocyclic, and unsubstituted or substituted 5-12 membered heteroaryl; or R 2 and R 3 may combine with an atom or atoms to which they are attached to form unsubstituted or substituted C 3-12 cycloalkyl, unsubstituted or substituted 3- to 12-membered heterocyclic, unsubstituted or substituted C 6-12 aryl, or unsubstituted or substituted 5- to 12-membered heteroaryl;

Y 1 , Y 2 , Y 3 , Y 4 , Y 5 , Y 6 , Y 7 and Y 8 are independently selected from the group consisting of hydrogen, halogen, unsubstituted or substituted alkyl, unsubstituted or substituted alkenyl, unsubstituted or substituted alkynyl, unsubstituted or substituted C 3-12 cycloalkyl, unsubstituted or substituted C 6-12 aryl, unsubstituted or substituted 3-12 membered heterocyclic, and unsubstituted or substituted 5-12 membered heteroaryl; and

L is selected from the group consisting of unsubstituted or substituted alkyl, unsubstituted or substituted C 6-12 aryl, and unsubstituted or substituted 3- to 12-membered heterocyclyl.

2. The method of claim 1 , wherein the metal layer has a flat topography, a convex topography, or a concave topography.

3. The method of claim 2 , wherein the flat topography has a diameter ranging from about 5 microns to about 250 microns.

4. The method of claim 1 , wherein the substrate has a diameter of 5 to 250 microns and an aspect ratio of 0.1 to 1.25, or a height of 5 to 300 microns.

5. The method of claim 4 , wherein the substrate has a recess having a height of 5 to 30 microns.

6. The method of claim 1 , wherein the substrate includes lines with a width of 10 nm to 20 microns, a length of 10 nm to 200 microns, and a thickness of 10 nm to 20 microns.

7. The method of claim 1 , wherein the substrate is a semiconductor wafer or chip.

8. The method of claim 1 , wherein R 1 in formula (I) is O.

9. The method of claim 1 , wherein Y 1 , Y 2 , Y 3 , Y 4 , Y 5 , Y 6 , Y 7 , and Y 8 in formula (I) are hydrogen.

10. The method of claim 1 , wherein R 2 , R 3 and R 4 in formula (I) are each independently C 1-6 alkyl.

11. The method of claim 1 , wherein R 2 in formula (I) is methyl, and R 3 and R 4 in formula (I) are isopropyl.

12. The method of claim 1 , wherein in R 2 and R 3 in formula (I) are ethyl, and R 4 in formula (I) is benzyl.

13. The method of claim 1 , wherein the electrolytic plating composition further includes an accelerator and a suppressor.

14. The method of claim 13 , wherein the accelerator is of formula (IV):

wherein X is O or S;

n is 1 to 6;

M is hydrogen, alkali metal, or ammonium;

R 1 is an alkylene, cyclic alkylene group of 1 to 8 carbon atoms, or an aromatic hydrocarbon of 6 to 12 carbon atoms; and

R 2 is MO 3 SR 1 .

15. The method of claim 14 , wherein X in formula (IV) is S.

16. The method of claim 13 , wherein the suppressor is of formula (VIII):

H 3 C—(CH 2 ) 3 —(OC 3 H 6 ) m /(OC 2 H 4 ) n —  (VIII)

wherein n is between 1 and about 200 and m is between 1 and about 200.