Gate driving module and gate-in-panel

1. A gate driving module comprising:

a first pull-up TFT having a terminal connected to a gate driving signal generator and another terminal connected to an end of a first gate line;

a first pull-down TFT having a terminal connected to the end of the first gate line and another terminal connected to a low-level voltage terminal;

a second pull-up TFT having a terminal connected to the gate driving signal generator and having another terminal, an another end opposite to the end of the first gate line connected only to the another terminal of the second pull-up TFT;

a third pull-up TFT having a terminal connected to the gate driving signal generator and another terminal connected to an end of a second gate line; and

a Q b 3 node connected to a gate terminal of the third pull-up TFT via a third inverter,

wherein the first pull-down TFT is turned off when the first pull-up TFT and the second pull-up TFT are turned on, and the first pull-down TFT is turned on when the first pull-up TFT and the second pull-up TFT are turned off, and

wherein the Q b 3 node is connected to a Q b 2 node, the Q b 2 node being connected to a gate terminal of the second pull-up TFT via a second inverter.

2. The gate driving module of claim 1 , wherein a gate driving signal generated by the gate driving signal generator is applied to the first gate line via the first pull-up TFT and the second pull-up TFT when the first pull-up TFT and the second pull-up TFT are turned on while the first pull-down TFT is turned off.

3. The gate driving module of claim 2 , wherein the first gate line is connected to a pixel structure, the pixel structure comprising a data line, a scan transistor, a capacitor, and a driving transistor,

wherein when the gate driving signal is applied to the first gate line, the scan transistor is turned on, and a data voltage is sequentially applied to the data line and to a gate terminal of the driving transistor via the scan transistor to turn on an organic light-emitting diode (OLED) connected to the transistor.

4. The gate driving module of claim 1 , wherein a low-level voltage signal is applied to the first gate line via the first pull-down TFT when the first pull-up TFT and the second pull-up TFT are turned off while the first pull-down TFT is turned on.

5. The gate driving module of claim 1 , further comprising: a first inverter having a terminal connected to a gate terminal of the first pull-up TFT and another terminal connected to a gate terminal of the first pull-down TFT.

6. The gate driving module of claim 5 , wherein the first inverter inverts a signal applied to the first pull-up TFT and the second pull-up TFT and outputs the inverted signal to the first pull-down TFT.

7. An organic light-emitting diode (OLED) display including the gate driving module of claim 1 .

8. A gate-in-panel comprising:

a first pull-up TFT having a terminal connected to a gate driving signal generator and another terminal connected to an end of a first gate line;

a first pull-down TFT having a terminal connected to the end of the first gate line and another terminal connected to a low-level voltage terminal;

a second pull-up TFT having a terminal connected to the gate driving signal generator and having another terminal, an another end opposite to the end of the first gate line connected only to the another terminal of the second pull-up TFT;

an active area in which a scan operation is carried out by a gate driving signal generated by the gate driving signal generator and applied via the first gate line;

a third pull-up TFT having a terminal connected to the gate driving signal generator and another terminal connected to an end of a second gate line; and

a Q b 3 node connected to a gate terminal of the third pull-up TFT via a third inverter,

wherein the first pull-down TFT is turned off when the first pull-up TFT and the second pull-up TFT are turned on, and the first pull-down TFT is turned on when the first pull-up TFT and the second pull-up TFT are turned off, and

wherein the Q b 3 node is connected to a Q b 2 node, the Q b 2 node being connected to a gate terminal of the second pull-up TFT via a second inverter.

9. The gate-in-panel of claim 8 , wherein the gate driving signal is applied to the first gate line via the first pull-up TFT and the second pull-up TFT when the first pull-up TFT and the second pull-up TFT are turned on while the first pull-down TFT is turned off.

10. The gate-in-panel of claim 9 , wherein the first gate line is connected to a pixel structure, the pixel structure comprising a data line, a scan transistor, a capacitor, and a driving transistor,

wherein when the gate driving signal is applied to the first gate line, the scan transistor is turned on, and a data voltage is sequentially applied to the data line and to a gate terminal of the driving transistor via the scan transistor to turn on an organic light-emitting diode (OLED) connected to the transistor.

11. The gate-in-panel of claim 8 , wherein a low-level voltage signal is applied to the first gate line via the first pull-down TFT when the first pull-up TFT and the second pull-up TFT are turned off while the first pull-down TFT is turned on.

12. The gate-in-panel of claim 8 , further comprising: a first inverter having a terminal connected to a gate terminal of the first pull-up TFT and another terminal connected to a gate terminal of the first pull-down TFT.

13. The gate-in-panel of claim 12 , wherein the first inverter inverts a signal applied to the first pull-up TFT and the second pull-up TFT and outputs the inverted signal to the first pull-down TFT.

14. An organic light-emitting diode (OLED) display including the gate-in-panel of claim 8 .