Sigma-delta analog-to-digital converter including loop filter having components for feedback digital-to-analog converter correction

1. An apparatus comprising:

an integrator in a loop filter of an analog-to-digital converter (ADC);

a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator; and

a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC, the loop filter including an additional integrator, and an additional DAC located on the feedback path of the ADC, the additional DAC including output nodes coupled to input nodes of the additional integrator.

2. The apparatus of claim 1 , wherein the comparator is part of comparator circuitry of a quantizer coupled to the loop filter.

3. An apparatus comprising:

an integrator in a loop filter of an analog-to-digital converter (ADC);

a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator; and

a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC, wherein the loop filter further includes:

an additional integrator;

an additional DAC located on the feedback path of the ADC, the additional DAC including output nodes coupled to input nodes of the additional integrator; and

an additional comparator including input nodes to receive signals from output nodes the additional integrator, and an output node to provide information during calibration of the additional DAC.

4. The apparatus of claim 3 , further comprising calibration circuitry to calibrate a DAC cell of the DAC and a DAC cell of the additional DAC in parallel.

5. The apparatus of claim 1 , further comprising a current source coupled to one of the input nodes of the integrator, and an amplifier to control the current source based on voltages at the input nodes of the integrator.

6. The apparatus of claim 5 , further comprising an additional current source coupled to another one the input nodes of the integrator, wherein the amplifier is to control the additional current source based on the voltages at the input nodes of the integrator.

7. The apparatus of claim 1 , wherein the DAC includes a DAC cell, the DAC cell including an adjustable current source, the adjustable current source including an array of transistors.

8. The apparatus of claim 7 , wherein the array of transistors is selected based on a combination of two voltages.

9. The apparatus of claim 8 , further comprising calibration circuitry to calibrate a DAC cell of the DAC during a first phase of calibration to obtain a first code, to calibrate the DAC cell of the DAC during a second phase of calibration to obtain a second code, and to generate an average of the first and second codes to control an adjustable current source of the DAC cell.

10. The apparatus of claim 1 , further comprising a counter to receive information from the comparator and generate a code to control an adjustable current of a DAC cell of the DAC.

11. The apparatus of claim 1 , further comprising calibration circuitry to toggle transistors of a DAC cell of the DAC during calibration of the DAC cell.

12. An apparatus comprising:

an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC);

a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, the DAC including DAC cells;

a comparator including input nodes to receive signals from output nodes of the integrator; and

logic circuitry to receive information from an output node of the comparator, the logic circuitry to provide a code to control an adjustable current source in one of the DAC cells, the loop filter including an additional integrator, and an additional DAC located on the feedback path of the ADC, the additional DAC including output nodes coupled to input nodes of the additional integrator.

13. The apparatus of claim 12 , wherein the output node of the comparator is coupled to an output circuit of a quantizer coupled to the loop filter.

14. The apparatus of claim 12 , wherein the adjustable current source includes a first group of transistors coupled in series between a node in the DAC cell and ground, a second group of transistors coupled in series between the node and ground; and a third group of transistors coupled in series between the node and ground.

15. The apparatus of claim 12 , wherein the logic circuitry includes a successive approximation register (SAR) logic to receive the information.

16. The apparatus of claim 15 , further comprising a selector to selectively provide codes from the SAR logic to the DAC cells.

17. The apparatus of claim 12 , further comprising calibration circuitry to toggle transistors of a DAC cell of the DAC at 50% duty cycle during calibration of the DAC cell.

18. The apparatus of claim 12 , wherein the DAC includes a current steering DAC.

19. An apparatus comprising:

an antenna; and

a receiver coupled to the antenna, the receiver including a sigma-delta analog-to-digital converter (ADC), the sigma-delta ADC including:

an integrator in a loop filter of an analog-to-digital converter (ADC);

a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator; and

a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC, the loop filter including an additional integrator, and an additional DAC located on the feedback path of the ADC, the additional DAC including output nodes coupled to input nodes of the additional integrator.

20. The apparatus of claim 19 , wherein the receiver is included in a front-end module circuitry of the apparatus.