Single or multi chip module package and related methods
Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.
1. A semiconductor device package consisting of:
at least one die comprising at least one electrical contact;
at least one clip comprising at least one electrical contact mechanically and electrically coupled with the at least one die;
one of an overmolding or an encapsulating compound comprised around the at least one die and a majority of the at least one clip, wherein the at least one electrical contact of the at least one die and the electrical contact of the at least one clip are not one of overmolded and encapsulated;
wherein the at least one electrical contact of the at least one die and the electrical contact of the at least one clip are configured to be positioned to electrically couple with one or more conductive paths comprised in a motherboard, the one or more conductive paths forming a distribution layer;
wherein the distribution layer is configured to distribute all electrical signals between the semiconductor device package and the motherboard; and
wherein the semiconductor device package comprises no lead frame.
2. A semiconductor device package comprising:
a plurality of electrical contacts comprised on a first face of a first die; and
one of a mold compound and an encapsulating compound comprised around the first die, wherein a portion of the plurality of electrical contacts on the first face of the first die are not one of overmolded and encapsulated;
wherein the portion of the plurality of electrical contacts on the first face of the first die are configured to be positioned to electrically couple with one or more conductive paths comprised in a motherboard, the one or more conductive paths forming a distribution layer; and
wherein the distribution layer is configured to distribute all electrical signals between the semiconductor device package and the motherboard;
wherein the semiconductor device package comprises no lead frame.
3. The semiconductor device package of claim 2 , further comprising at least one electrical contact on a first face of a second die; and
a first clip mechanically and electrically coupled with an electrical contact on a second face of the second die where the second face of the second die is on an opposing side of the second die from the first face of the second die;
wherein one of a mold compound and an encapsulating compound enclose the second die and a majority of the first clip; and
wherein the at least one electrical contact on the first face of the second die and the electrical contact of the first clip are not one of overmolded and encapsulated.
4. The semiconductor device package of claim 3 , wherein the first clip is one of bonded and soldered to the second face of the second die.
5. The semiconductor device package of claim 3 , wherein the distribution layer is configured to distribute all electrical communication among and between each die, each clip and each passive component of the semiconductor device package and to further interconnect one or more components of the semiconductor device package with one or more components external to the semiconductor package through one or more conductive paths of the motherboard.
6. The semiconductor device package of claim 3 , further comprising:
at least one electrical contact on a first face of a third die;
a second clip mechanically and electrically coupled with an electrical contact on a second face of the third die, the second face of the third die on an opposing side of the third die from the first face of the third die;
wherein the third die and a majority of the second clip are one of overmolded and encapsulated; and
wherein the at least one electrical contact on the first face of the third die and the electrical contact of the second clip are not one of overmolded and encapsulated.
7. The semiconductor device package of claim 6 , wherein the distribution layer is configured to distribute all electrical communication between the first die, the second die and the third die.
8. The semiconductor device package of claim 6 , wherein the second clip is positioned to electrically couple the second die with the third die through the one or more conductive paths comprised in the motherboard.
9. The semiconductor device package of claim 6 , wherein the electrical contact of the second clip is positioned to electrically couple with the one or more conductive paths comprised in the motherboard.
10. The semiconductor device package of claim 2 , wherein the semiconductor device package comprises no wire bonds.
11. The semiconductor device package of claim 2 , wherein the distribution layer is configured to distribute a majority of electrical signals between the plurality of electrical contacts on the first face of the first die.
12. A semiconductor device package comprising:
a plurality of electrical contacts on a first face of one of a first die;
a passive component;
one of a mold compound and an encapsulating compound comprised around the first die and passive component, wherein a portion of the plurality of electrical contacts on the first face of one of the first die and passive component are not one of overmolded and encapsulated;
wherein the portion of the plurality of electrical contacts on the first face of one of the first die and passive component are configured to be positioned to electrically couple with one or more conductive paths comprised in a motherboard, the one or more conductive paths forming a distribution layer;
wherein the distribution layer is configured to distribute all electrical signals between the semiconductor package and the motherboard; and
wherein the semiconductor device packages comprises no lead frame.
13. The semiconductor device package of claim 12 , further comprising no wire bonds.
14. A semiconductor device package, consisting essentially of:
a plurality of electrical contacts on a first face of a die;
at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die, the second face of the die on an opposing side of the die from the first face of the die, the at least one clip comprising at least one lead in electrical communication with the at least one electrical contact on the second face of the die; and
one of a mold compound and an encapsulating compound comprised around the die and a majority of the at least one clip, wherein a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not one of overmolded and encapsulated;
wherein the semiconductor package comprises no lead frame.
15. The semiconductor device package of claim 14 , wherein the plurality of electrical contacts on the first face of the die comprise one of pads and bumps.
16. The semiconductor device package of claim 14 , wherein the semiconductor device package comprises no wire bonds.
17. The semiconductor device package of claim 14 , wherein the at least one clip is mechanically coupled with the at least one electrical contact through of one bonding and soldering on the second face of the die.