IP Library Granted Patent US 9,954,168
Granted Patent B2
US 9,954,168 · App. 15/392,399 · Granted Apr 24, 2018

Semiconductor memory device and method for manufacturing same

Inventor: Kotaro Noda (Mie-ken, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L45/1675H01L27/2409H01L27/2481H01L45/085H01L45/1233H01L45/1266H01L45/146H01L45/148
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Quick Facts
Patent No.
US 9,954,168
App. No.
15/392,399
Granted
Apr 24, 2018
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.

Claims (36)

1. A method for manufacturing a semiconductor memory device, comprising:

forming a plurality of stacked films to extend in a first direction to be respectively stacked on a plurality of first interconnects extending in the first direction, each of the plurality of stacked films including a variable resistance film;

forming a first inter-layer insulating film in a first region between the stacked films;

forming a second inter-layer insulating film in a second region having a wider width than the first region;

forming a plurality of second interconnects on the stacked films, on the first inter-layer insulating film, and on the second inter-layer insulating film to extend in a second direction crossing the first direction; and

etching the stacked films and the first inter-layer insulating film under a space between the second interconnects,

the second inter-layer insulating film under the space between the second interconnects being etched at an etching rate lower than an etching rate of the first inter-layer insulating film in the etching of the stacked films and the first inter-layer insulating film.

2. The method for manufacturing the semiconductor memory device according to claim 1 , wherein a bottom surface of a portion from which the second inter-layer insulating film is removed by the etching is at a position higher than a bottom surface of a portion from which the first inter-layer insulating film is removed by the etching.

3. The method for manufacturing the semiconductor memory device according to claim 1 , wherein

a portion of the first inter-layer insulating film is formed conformally in the second region; and

the second inter-layer insulating film is formed on the first inter-layer insulating film in the second region after the forming of the first inter-layer insulating film.

4. The method for manufacturing the semiconductor memory device according to claim 3 , wherein the first inter-layer insulating film is formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition).

5. The method for manufacturing the semiconductor memory device according to claim 1 , wherein

the first inter-layer insulating film and the second inter-layer insulating film include silicon oxide, and

the first inter-layer insulating film and the second inter-layer insulating film are etched by RIE (Reactive Ion Etching) using a gas including a fluorocarbon.

6. The method for manufacturing the semiconductor memory device according to claim 1 , wherein the stacked films and the first inter-layer insulating film are etched simultaneously.

7. A method for manufacturing a semiconductor memory device, comprising:

forming a first interconnect material and a stacked film including a plurality of films on the first interconnect material, the films including a variable resistance film;

forming a plurality of line portions of the first interconnect material and the stacked film by etching the first interconnect material and the stacked film, the line portions extending in a first direction crossing a stacking direction of the stacked film and arranged in a second direction crossing the stacking direction and the first direction;

burying a first insulating film between the line portions arranged in the second direction;

etching an outermost portion of the stacked film in a region outside the line portions arranged in the second direction;

burying a second insulating film in an etched portion of the outermost portion of the stacked film;

planarizing an upper surface of the stacked film, an upper surface of the first insulating film, and an upper surface of the second insulating film;

forming a second interconnect material on the planarized upper surface of the stacked film, the planarized upper surface of the first insulating film, and the planarized upper surface of the second insulating film; and

at least partly etching the second interconnect material, the stacked film, the first insulating film and the second insulating film so as to remain a plurality of line portions extending in the second direction and arranged in the first direction, a bottom surface of a portion wherein the second insulating film is removed being higher than a bottom surface of a portion wherein the first insulating film is removed.

8. The method for manufacturing the semiconductor memory device according to claim 7 , wherein a composition of the first insulating film is different from a composition of the second insulating film.

9. The method for manufacturing the semiconductor memory device according to claim 7 , wherein an etching rate of the first insulating film is different from an etching rate of the second insulating film.

10. The method for manufacturing the semiconductor memory device according to claim 7 , further comprising burying a film between the line portions of the second interconnect and the stacked film arranged in the first direction, the film having a same material as the first insulating film.

11. The method for manufacturing the semiconductor memory device according to claim 7 , wherein

a portion of the first insulating film is formed conformally in the etched portion of the outermost portion of the stacked film, and

the second insulating film is formed on the first insulating film in the etched portion of the outermost portion of the stacked film.

12. The method for manufacturing the semiconductor memory device according to claim 11 , wherein the first insulating film is formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition).

13. The method for manufacturing the semiconductor memory device according to claim 7 , wherein

the first insulating film and the second insulating film include silicon oxide, and

the first insulating film and the second insulating film are etched by RIE (Reactive Ion Etching) using a gas including a fluorocarbon.

14. The method for manufacturing the semiconductor memory device according to claim 7 , wherein the line portions arranged in the second direction and the first insulating film between the line portions arranged in the second direction are etched simultaneously.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
Continuity (3)
Division 13939738 · Jul 11, 2013
Provisional Application 61770520 · Feb 28, 2013
Related Publication 20170110659A1 · Apr 20, 2017