Differential sensing circuit of a floating voltage source

1. A circuit, comprising:

a first voltage divider coupled between a first voltage level and a ground potential;

an error amplifier having a first input terminal coupled to a node between a first resistive element and a second resistive element of the first voltage divider; and

a second voltage divider coupled between a second voltage level and a reference voltage, wherein a second input terminal of the error amplifier is coupled to a node between a third resistive element and a fourth resistive element of the second voltage divider, and wherein an output voltage of the error amplifier is configured to control a potential difference between the first voltage level and the second voltage level.

2. The circuit of claim 1 , wherein a first terminal and a second terminal of the third resistive element are coupled to the second voltage level and the second input terminal of the error amplifier, respectively, and wherein a first terminal and a second terminal of the fourth resistive element are coupled to the second input terminal of the error amplifier and the reference voltage, respectively.

3. The circuit of claim 2 , further comprising a voltage buffer configured to provide the reference voltage to the second terminal of the fourth resistive element.

4. The circuit of claim 1 , wherein a first terminal and a second terminal of the first resistive element are coupled to the first voltage level and the first input terminal of the error amplifier, respectively, and wherein a first terminal and a second terminal of the second resistive element are coupled to the first input terminal of the error amplifier and the ground potential, respectively.

5. The circuit of claim 1 , wherein the potential difference between the first voltage level and the second voltage level is substantially equal to the reference voltage multiplied by a gain factor.

6. The circuit of claim 5 , wherein the gain factor is substantially equal to a ratio of a resistance of the first resistive element to a resistance of the second resistive element.

7. The circuit of claim 1 , wherein a resistance of the first resistive element is equal to a resistance of the third resistive element, and wherein a resistance of the second resistive element is equal to a resistance of the fourth resistive element.

8. The circuit of claim 1 , further comprising:

a load resistor coupled between the first voltage level and the second voltage level; and

a pass transistor having a gate terminal coupled to an output terminal of the error amplifier, the pass transistor configured to cause a current to flow through the load resistor based on the output voltage of the error amplifier.

9. A circuit, comprising:

an amplifier having a first input terminal and a second input terminal;

a first resistive element coupled between the first input terminal and a first voltage level;

a second resistive element coupled between the first input terminal and a ground potential;

a third resistive element coupled between the second input terminal and a second voltage level different from the first voltage level;

a fourth resistive element coupled between the second input terminal and a non-zero reference voltage;

a load resistor coupled between the first voltage level and the second voltage level; and

a pass transistor having a gate terminal coupled to an output terminal of the amplifier, wherein the pass transistor is configured to cause a current to flow through the load resistor in response to a voltage at the output terminal of the amplifier.

10. The circuit of claim 9 , wherein the first input terminal and the second input terminal of the amplifier comprise a non-inverting input and an inverting input of the amplifier, respectively.

11. The circuit of claim 9 , wherein the first voltage level is between about 20 V and about 25 V.

12. The circuit of claim 9 , wherein a potential difference between the first voltage level and the second voltage level is between about 2 V and about 3V.

13. The circuit of claim 9 , further comprising:

a first capacitive element coupled in parallel to the first resistive element;

a second capacitive element coupled in parallel to the second resistive element;

a third capacitive element coupled in parallel to the third resistive element; and

a fourth capacitive element coupled in parallel to the fourth resistive element.

14. The circuit of claim 13 , wherein a capacitance of the first capacitive element is equal to a capacitance of the third capacitive element, and wherein a capacitance of the second capacitive element is equal to a capacitance of the fourth capacitive element.

15. The circuit of claim 13 , wherein a resistance of the first resistive element is equal to a resistance of the third resistive element, and wherein a resistance of the second resistive element is equal to a resistance of the fourth resistive element.

16. The circuit of claim 13 , wherein a ratio of a capacitance of the first capacitive element to a capacitance of the second capacitive element is equal to a ratio of a resistance of the first resistive element to a resistance of the second resistive element.

17. The circuit of claim 9 , further comprising a voltage buffer configured to output the non-zero reference voltage to a terminal of the fourth resistive element.

18. A method, comprising:

providing a first voltage to a first input terminal of an error amplifier, the first voltage being determined based on a first voltage divider circuit coupled between a first voltage level and a ground potential;

providing a second voltage to a second input terminal of the error amplifier, the second voltage being determined based on a second voltage divider circuit coupled between a second voltage level and a non-zero reference voltage different from the ground potential; and

regulating a potential difference between the first voltage level and the second voltage level based on the first voltage being equal to the second voltage.

19. The method of claim 18 , wherein the first input terminal and the second input terminal of the error amplifier comprise a non-inverting terminal and an inverting terminal of the error amplifier, respectively.

20. The method of claim 18 , wherein the potential difference between the first voltage level and the second voltage level is regulated to be between about 2 V and about 3 V.

21. The method of claim 18 , further comprising:

buffering the non-zero reference voltage at an output terminal of a voltage follower; and

providing the non-zero reference voltage to a terminal of the second voltage divider circuit.