Technique to share information among different cache coherency domains

1. A system comprising:

a plurality of processors;

a system memory coupled to one or more of the processors over a memory interface circuit;

a first interconnect circuit to couple at least two of the plurality of processors;

at least one of the processors comprising:

a plurality of cores having a first processing architecture;

a first level cache, a second level cache, and a third level cache configured in a cache hierarchy within a cache coherency domain usable by at least one of the cores, at least one cache of the cache hierarchy to store information to be shared with one or more functional circuits having a second processing architecture;

a communication interconnect circuit to couple one or more of the plurality of cores to the one or more functional circuits over at least one bus; and

cache coherence circuitry to maintain coherence between at least one cache within the cache coherency domain of the at least one core and at least one cache of the one or more functional circuits;

wherein the cache coherence circuitry is to transfer information provided by at least one core within the cache hierarchy to make the information accessible to the at least one cache of the one or more of the functional circuits, and

wherein the cache coherence circuitry is to transfer information generated or modified by one or more of the functional circuits to make the information accessible to at least one cache of the cache hierarchy.

2. The system as in claim 1 wherein the plurality of cores are formed on a first die and the one or more functional circuits are formed on a second die.

3. The system as in claim 1 wherein the communication interconnect circuit comprises a PCI express (PCIe) communication interface.

4. The system as in claim 1 wherein the one or more functional circuits are to perform one or more of: graphics processing functions, memory control functions, peripheral control functions, audio functions, video functions, disk control functions, and/or digital signal processing functions.

5. The system as in claim 1 wherein at least one of the functional circuits comprises a graphics processing circuit.

6. The system as in claim 1 wherein the cache coherency circuit is to maintain coherence by processing snoop operations.

7. The system as in claim 6 wherein the snoop operations are initiated by the cores or by the functional circuits.

8. The system as in claim 1 further comprising:

at least one storage device coupled to at least one of the processors.

9. The system as in claim 1 further comprising:

at least one communication device coupled to at least one of the processors.

10. The system as in claim 1 wherein the system memory comprises a dynamic random access memory (DRAM).

11. The system as in claim 1 wherein the first interconnect circuit comprises a point-to-point (P2P) interconnect.

12. The system as in claim 1 wherein the first interconnect circuit comprises a ring interconnect.

13. A system comprising:

a plurality of processors;

system memory means coupled to one or more of the processors over a memory interface means;

first interconnect means to couple at least two of the plurality of processors;

at least one of the processors comprising:

means for storing information in at least one cache of a cache hierarchy accessible by one or more cores having a first processing architecture, the information to be shared with one or more functional circuits having a second processing architecture, the cache hierarchy including a first level cache, a second level cache, and a third level cache within a cache coherency domain usable by at least one of the cores;

means for coupling one or more of the plurality of cores to the one or more functional circuits; and

means for maintaining coherence between at least one cache within the cache coherency domain of the at least one core and at least one cache of the one or more functional circuits;

wherein maintaining coherence comprises transferring information provided by at least one core within the cache hierarchy to make the information accessible to the at least one cache of the one or more of the functional circuits, and

transferring information generated or modified by one or more of the functional circuits to make the information accessible to at least one cache of the cache hierarchy.

14. The system as in claim 13 wherein the plurality of cores are formed on a first die and the one or more functional circuits are formed on a second die.

15. The system as in claim 13 wherein the communication interconnect circuit comprises a PCI express (PCIe) communication interface.

16. The system as in claim 13 wherein the one or more functional circuits are to perform one or more of: graphics processing functions, memory control functions, peripheral control functions, audio functions, video functions, disk control functions, and/or digital signal processing functions.

17. The system as in claim 13 wherein at least one of the functional circuits comprises a graphics processing circuit.

18. The system as in claim 13 wherein maintaining coherence comprises processing snoop operations.

19. The system as in claim 18 wherein the snoop operations are initiated by the cores or by the functional circuits.

20. The system as in claim 13 further comprising:

at least one storage device coupled to at least one of the processors.

21. The system as in claim 13 further comprising:

at least one communication device coupled to at least one of the processors.

22. The system as in claim 13 wherein the system memory comprises a dynamic random access memory (DRAM).

23. The system as in claim 13 wherein the first interconnect circuit comprises a point-to-point (P2P) interconnect.

24. The system as in claim 13 wherein the first interconnect circuit comprises a ring interconnect.