IP Library Granted Patent US 10,338,983
Granted Patent B2
US 10,338,983 · App. 15/395,248 · Granted Jul 2, 2019

Method and system for online program/erase count estimation

Inventors: Seungjune Jeon (Santa Clara, CA); Haleh Tabrizi (San Francisco, CA); Andrew Cullen (Cork, IE)
Assignee: EMC IP Holding Company LLC
G06F11/076G06F3/0619G06F3/0652G06F3/0653G06F3/0658G06F3/0679G06F11/079G06F11/0727
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Quick Facts
Patent No.
US 10,338,983
App. No.
15/395,248
Granted
Jul 2, 2019
Kind
B2
Abstract

In general, the technology relates to a method for managing persistent storage. The method includes selecting a sample set of physical addresses in a solid state memory module, and performing a garbage collection operation on the sample set of physical addresses. The method further includes, after the garbage collection operation, issuing a write request to the sample set of physical addresses, issuing a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses, determining an error rate in the copy of the data stored using an Error Correction Code codeword or known data in the write request, determining a calculated P/E cycle value for the SSMM using at least the error rate, and updating an in-memory data structure in a control module with the calculated P/E cycle value.

Claims (41)

1. A method for managing persistent storage, the method comprising:

selecting a sample set of physical addresses in a solid state memory module (SSMM), wherein the sample set of physical addresses is associated with a region in the SSMM;

performing a garbage collection operation on the sample set of physical addresses;

after the garbage collection operation, issuing a write request to the sample set of physical addresses;

after issuing the write request, issuing a read request to the sample set of physical addresses to obtain a copy of data stored in the sample set of physical addresses;

determining an error rate in the copy of the data stored using at least one selected from a group consisting of an Error Correction Code (ECC) codeword and, known data in the write request;

determining a calculated P/E cycle value for the SSMM using at least the error rate; and

updating an in-memory data structure in a control module with the calculated P/E cycle value.

2. The method of claim 1 , further comprising:

servicing at least one read request using the calculated P/E cycle value.

3. The method of claim 1 , further comprising:

prior to the selecting:

determining that the region in the SSMM is not associated with a P/E cycle value.

4. The method of claim 1 , further comprising:

prior to the selecting:

detecting a P/E cycle value anomaly in a P/E cycle value associated with the region.

5. The method of claim 4 , wherein detecting the P/E cycle value anomaly comprises determining that a difference in the P/E cycle value for the region and a P/E cycle value for a second region in the SSMM is greater than an anomaly threshold.

6. The method of claim 1 , further comprising:

servicing at least one selected from a group consisting of a read request and a write request by the SSMM while determining the error rate.

7. The method of claim 1 , wherein the error rate is a failed bit count (FBC).

8. The method of claim 7 , wherein the FBC is a mean FBC of all FBCs determined from the copy of the data.

9. The method of claim 1 , wherein the SSMM is one of a plurality of SSMM in a storage module.

10. The method of claim 1 , wherein the SSMM comprises NAND flash.

11. The method of claim 1 , wherein performing the garbage collection operation on the sample set of physical addresses comprises:

determining that data stored in a physical address in the sample set of physical addresses is live;

selecting a new physical address, wherein the new physical address is associated with a known P/E cycle value; and

storing a copy of the data at the new physical address.

12. The method of claim 11 , wherein the new physical address is located in a second SSMM in a second storage module, wherein the SSMM is located in a storage module.

13. The method of claim 1 , wherein the calculated P/E cycle value represents a P/E cycle value range.

14. A non-transitory computer readable medium comprising computer readable program code, which when executed by a computer processor enables the computer processor to:

select a sample set of physical addresses in a solid state memory module (SSMM), wherein the sample set of physical addresses is associated with a region in the SSMM;

perform a garbage collection operation on the sample set of physical addresses;

after the garbage collection operation, issue a write request to the sample set of physical addresses;

after issuing the write request, issue a read request to the sample set of physical addresses to obtain a copy of data stored in the sample set of physical addresses;

determine an error rate in the copy of the data stored using at least one selected from a group consisting of an Error Correction Code (ECC) codeword and, known data in the write request;

determine a calculated P/E cycle value for the SSMM using at least the error rate; and

update an in-memory data structure in a control module with the calculated P/E cycle value.

15. The non-transitory computer readable medium of claim 14 further comprising computer readable program code, which when executed by the computer processor enables the computer processor to:

service at least one read request using the calculated P/E cycle value.

16. The non-transitory computer readable medium of claim 14 further comprising computer readable program code, which when executed by the computer processor enables the computer processor to:

service at least one selected from a group consisting of a read request and a write request by the SSMM while determining the error rate.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST AT REEL 048825 FRAME 0489 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058000/0916 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Apr 8, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 048825/0489 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2017
From: JEON, SEUNGJUNE; TABRIZI, HALEH; CULLEN, ANDREW
To: EMC IP HOLDING COMPANY
Reel/Frame 044331/0010 →
Continuity (1)
Related Publication 20180189123A1 · Jul 5, 2018