IP Library › Granted Patent US 9,786,648
Granted Patent B1
US 9,786,648 · App. 15/395,833 · Granted Oct 10, 2017

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

Inventors: Stephen Lam (Freemont, CA); Dennis Ciplickas (San Jose, CA); Tomasz Brozek (Morgan Hill, CA); Jeremy Cheng (San Jose, CA); Simone Comensoli (Darfo Boario Terme, IT); Indranil De (Mountain View, CA); Kelvin Doong (Hsinchu, TW); Hans Eisenmann (Tutzing, DE); Timothy Fiscus (New Galilee, PA); Jonathan Haigh (Pittsburgh, PA); Christopher Hess (Belmont, CA); John Kibarian (Los Altos Hills, CA); Sherry Lee (Monte Sereno, CA); Marci Liao (Santa Clara, CA); Sheng-Che Lin (Hsinchu, TW); Hideki Matsuhashi (Santa Clara, CA); Kimon Michaels (Monte Sereno, CA); Conor O'Sullivan (Campbell, CA); Markus Rauscher (Munich, DE); Vyacheslav Rovner (Pittsburgh, PA); Andrzej Strojwas (Pittsburgh, PA); Marcin Strojwas (Pittsburgh, PA); Carl Taylor (Pittsburgh, PA); Rakesh Vallishayee (Dublin, CA); Larg Weiland (Hollister, CA); Nobuharu Yokoyama (Tokyo, JP)
Assignee: PDF Solutions, Inc.
H01L27/0207H01L22/26H01L22/34H01L23/528H01L29/41725G06F11/079G06F17/5045G06F17/5072G06F17/5081H01L29/0684
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Quick Facts
Patent No.
US 9,786,648
App. No.
15/395,833
Granted
Oct 10, 2017
Kind
B1
Abstract

An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of short-circuit failure modes, including at least one chamfer-short-related failure mode, one AACNT-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.

Claims (103)

1. A monolithic integrated circuit (1C) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V0) layer, a first wiring (M1) layer, a second wiring (M2) layer, and an M1-to-M2 via (VI) layer, said 1C comprising at least:

(i) a plurality of logic cells selected from a standard cell library in which each logic cell has a height, supply rail configuration, and GATE pitch (CPP) configured for abutted instantiation with other logic cells in the library; and,

(ii) a plurality of at least four different, non-contact electrical measurement (NCEM)-enabled fill cells, each of said NCEM-enabled fill cells having a height, supply rail configuration, and CPP configured for abutted instantiation with logic cells in the standard cell library, said plurality of NCEM-enabled fill cells including:

(a) at least one chamfer-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test area patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves a via chamfering;

(b) at least one AACNT-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves the AACNT layer;

(c) at least one GATECNT-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves the GATECNT layer; and,

(d) at least one TS-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves the TS layer.

2. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V0-AACNT-chamfer-short-configured, NCEM-enabled fill cell.

3. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V3-M3-chamfer-short-configured, NCEM-enabled fill cell.

4. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cell.

5. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V1-M1-via-chamfer-short-configured, NCEM-enabled fill cell.

6. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V2-M2-via-chamfer-short-configured, NCEM-enabled fill cell.

7. A monolithic IC, as defined in claim 1 , wherein the at least one AACNT-short-configured, NCEM-enabled fill cell comprises a V0-AACNT-chamfer-short-configured, NCEM-enabled fill cell.

8. A monolithic IC, as defined in claim 1 , wherein the at least one AACNT-short-configured, NCEM-enabled fill cell comprises an AACNT-tip-to-tip-short-configured, NCEM-enabled fill cell.

9. A monolithic IC, as defined in claim 1 , wherein the at least one AACNT-short-configured, NCEM-enabled fill cell comprises at least one of:

an AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cell;

an AACNT-tip-to-side-short-configured, NCEM-enabled fill cell;

an AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cell;

an AACNT-side-to-side-short-configured, NCEM-enabled fill cell;

an AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cell;

an AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cell;

an AACNT-diagonal-short-configured, NCEM-enabled fill cell;

an AACNT-AA-diagonal-short-configured, NCEM-enabled fill cell;

a GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cell;

an AACNT-corner-short-configured, NCEM-enabled fill cell;

an AACNT-AA-corner-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cell;

a GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cell;

an M1-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cell; and/or, an AACNT-via-chamfer-short-configured, NCEM-enabled fill cell.

10. A monolithic IC, as defined in claim 1 , wherein the at least one GATECNT-short-configured, NCEM-enabled fill cell comprises a GATECNT-TS-corner-short-configured, NCEM-enabled fill cell.

11. A monolithic IC, as defined in claim 1 , wherein the at least one GATECNT-short-configured, NCEM-enabled fill cell comprises a GATECNT-tip-to-tip-short-configured, NCEM-enabled fill cell.

12. A monolithic IC, as defined in claim 1 , wherein the at least one GATECNT-short-configured, NCEM-enabled fill cell comprises at least one of:

a GATECNT-GATE-tip-to-tip-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cell;

a GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-tip-to-side-short-configured, NCEM-enabled fill cell;

a TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-side-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-GATE-diagonal-short-configured, NCEM-enabled fill cell;

a GATECNT-diagonal-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cell;

a GATECNT-GATE-corner-short-configured, NCEM-enabled fill cell;

a GATECNT-corner-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cell;

a GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell;

a GATECNT-AA-interlayer-overlap-short-configured, NCEM-enabled fill cell;

an M1-GATECNT-interlayer-overlap-short-configured, NCEM-enabled fill cell; and/or,

a V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cell.

13. A monolithic IC, as defined in claim 1 , wherein the at least one TS-short-configured, NCEM-enabled fill cell comprises a GATECNT-TS-corner-short-configured, NCEM-enabled fill cell.

14. A monolithic IC, as defined in claim 1 , wherein the at least one TS-short-configured, NCEM-enabled fill cell comprises TS-GATE-side-to-side-short-configured, NCEM-enabled fill cell.

15. A monolithic IC, as defined in claim 1 , wherein the at least one TS-short-configured, NCEM-enabled fill cell comprises at least one of:

an AACNT-TS-tip-to-tip-short-configured, NCEM-enabled fill cell;

a TS-tip-to-tip-short-configured, NCEM-enabled fill cell;

a TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cell;

a GATECNT-AACNT-TS-tip-to-side-short-configured, NCEM-enabled fill cell;

a TS-diagonal-short-configured, NCEM-enabled fill cell;

a GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell;

a GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell; and/or,

a V0-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell.

16. A monolithic IC, as defined in claim 1 , wherein at least two of the (b) at least one AACNT-short-configured, (c) at least one GATECNT-short-configured, and (d) at least one TS-short-configured, NCEM-enabled fill cells are of the same color variety.

17. A monolithic IC, as defined in claim 1 , wherein each of the (b) at least one AACNT-short-configured, (c) at least one GATECNT-short-configured, and (d) at least one TS-short-configured, NCEM-enabled fill cells is of the same color variety.

18. A monolithic IC, as defined in claim 1 , wherein at least one of the (b) at least one AACNT-short-configured, (c) at least one GATECNT-short-configured, and (d) at least one TS-short-configured, NCEM-enabled fill cells is of the different color variety.

19. A monolithic IC, as defined in claim 1 , wherein each of the (b) at least one AACNT-short-configured, (c) at least one GATECNT-short-configured, and (d) at least one TS-short-configured, NCEM-enabled fill cells includes an M1 pad.

20. A monolithic IC, as defined in claim 1 , wherein the IC includes at least one additional NCEM-enabled fill cell selected from the list consisting of:

GATECNT-GATE-via-open-configured, NCEM-enabled fill cells;

M1-V0-via-open-configured, NCEM-enabled fill cells;

M1-corner-short-configured, NCEM-enabled fill cells;

AACNT-AA-via-open-configured, NCEM-enabled fill cells;

V0-GATECNT-via-open-configured, NCEM-enabled fill cells;

V0-merged-via-open-configured, NCEM-enabled fill cells;

GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-TS-via-open-configured, NCEM-enabled fill cells;

GATE-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-via-open-configured, NCEM-enabled fill cells;

M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V0-AACNT-via-open-configured, NCEM-enabled fill cells;

AA-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATE-side-to-side-short-configured, NCEM-enabled fill cells;

M1-side-to-side-short-configured, NCEM-enabled fill cells;

M4-V3-via-open-configured, NCEM-enabled fill cells;

M1-snake-open-configured, NCEM-enabled fill cells;

M3-V2-via-open-configured, NCEM-enabled fill cells;

M5-V4-via-open-configured, NCEM-enabled fill cells;

V1-M1-via-open-configured, NCEM-enabled fill cells;

GATECNT-AACNT-GATE-via-open-configured, NCEM-enabled fill cells;

TS-AA-via-open-configured, NCEM-enabled fill cells;

V0-via-open-configured, NCEM-enabled fill cells;

M1-stitch-open-configured, NCEM-enabled fill cells;

GATECNT-AACNT-via-open-configured, NCEM-enabled fill cells;

M1-V0-side-to-side-short-configured, NCEM-enabled fill cells;

GATE-snake-open-configured, NCEM-enabled fill cells;

M1-tip-to-tip-short-configured, NCEM-enabled fill cells;

M1-V0-AACNT-snake-open-configured, NCEM-enabled fill cells;

V1-via-open-configured, NCEM-enabled fill cells; and,

V3-via-open-configured, NCEM-enabled fill cells.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2017
From: LAM, STEPHEN; CIPLICKAS, DENNIS; BROZEK, TOMASZ; CHENG, JEREMY; COMENSOLI, SIMONE; DE, INDRANIL; DOONG, KELVIN; EISENMANN, HANS; FISCUS, TIMOTHY; HAIGH, JONATHAN; HESS, CHRISTOPHER; KIBARIAN, JOHN; LEE, SHERRY; LIAO, MARCI; LIN, SHENG-CHE; MATSUHASHI, HIDEKI; MICHAELS, KIMON; O'SULLIVAN, CONOR; RAUSCHER, MARKUS; ROVNER, VYACHESLAV; STROJWAS, ANDRZEJ; STROJWAS, MARCIN; TAYLOR, CARL; VALLISHAYEE, RAKESH; WEILAND, LARG; YOKOYAMA, NOBUHARU
To: PDF SOLUTIONS, INC.
Reel/Frame 040814/0824 →
Continuity (3)
Continuation 15090256 · Apr 4, 2016
Continuation 15090267 · Apr 4, 2016
Continuation 15090274 · Apr 4, 2016