IP Library Granted Patent US 10,362,149
Granted Patent B2
US 10,362,149 · App. 15/396,196 · Granted Jul 23, 2019

Intelligent packet aggregation

Inventors: Dan Biederman (Saratoga, CA); Michael Orr (Sunnyvale, CA)
Assignee: Intel Corporation
H04L69/22H04L12/4641H04L47/22H04L47/625H04L47/6275H04L49/9005H04L69/16H04L69/32H04L69/321
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Quick Facts
Patent No.
US 10,362,149
App. No.
15/396,196
Granted
Jul 23, 2019
Kind
B2
Abstract

Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.

Claims (55)

1. A network interface device for implementing intelligent packet aggregation, the network interface device comprising:

a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and

a coordinator circuit to:

interface with a processing element to determine a current operational state of the processing element;

select a first queue from the plurality of queues based on the current operational state of the processing element; and

forward a number of packets from the selected first queue to the processing element,

wherein to select the first queue from the plurality of queues, the coordinator circuit is to:

determine a current priority associated with each queue of a set of queues of the plurality of queues; and

select the first queue as the one with a highest priority of the current priorities of the set of queues from the set of queues; and

decrease the current priority of a second queue in the set of queues when the current operational state indicates that the processing element is not currently active and unable to process packets stored in the second queue.

2. The device of claim 1 , wherein the processing element comprises a virtual machine.

3. The device of claim 1 , wherein the processing element comprises a field-programmable gate array (FPGA) program.

4. The device of claim 1 , wherein the packet parser includes a TCP offload engine to inspect the plurality of packets.

5. The device of claim 1 , wherein the packet parser is to:

attempt to identify a queue of the plurality of queues that corresponds to a particular packet;

allocate a new queue when the identification fails; and

store the particular packet in the new queue.

6. The device of claim 1 , wherein the current operational state of the processing element comprises a current operating thread.

7. The device of claim 1 , wherein the current operational state of the processing element comprises a current operating process.

8. The device of claim 1 , wherein the current operational state of the processing element comprises a current operating virtual machine.

9. The device of claim 1 , wherein the current operational state of the processing element comprises a current FPGA configuration.

10. The device of claim 1 , wherein the current priority of the first queue is increased when the current operational state indicates that the processing element is able to process packets stored in the first queue.

11. The device of claim 1 , wherein to forward the number of packets from the selected first queue to the processing element, the coordinator circuit is to enforce a traffic regulation policy while forwarding the number of packets.

12. A method of implementing intelligent packet aggregation, the method comprising:

receiving, at a packet parser, a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics;

interfacing with a processing element to determine a current operational state of the processing element;

selecting a first queue from the plurality of queues based on the current operational state of the processing element; and

forwarding a number of packets from the selected first queue to the processing element,

wherein selecting the first queue from the plurality of queues comprises:

determining a current priority associated with each queue of a set of queues of the plurality of queues; and

selecting the first queue as the one with a highest priority of the current priorities of the set of queues from the set of queues; and

decreasing the current priority of a second queue in the set of queues when the current operational state indicates that the processing element is not currently active and unable to process packets stored in the second queue.

13. The method of claim 12 , wherein the packet parser includes a TCP offload engine to inspect the plurality of packets.

14. The method of claim 12 , further comprising:

attempting to identify a queue of the plurality of queues that corresponds to a particular packet;

allocating a new queue when the identification fails; and

storing the particular packet in the new queue.

15. The method of claim 12 , wherein the current operational state of the processing element comprises a current operating thread.

16. The method of claim 12 , wherein the current operational state of the processing element comprises a current operating process.

17. The method of claim 12 , wherein the current operational state of the processing element comprises a current operating virtual machine.

18. The method of claim 12 , wherein the current operational state of the processing element comprises a current FPGA configuration.

19. The method of claim 12 , wherein the current priority of the first queue is increased when the current operational state indicates that the processing element is able to process packets stored in the first queue.

20. At least one non-transitory machine-readable medium including instructions for implementing intelligent packet aggregation, which when executed by a machine, cause the machine to:

receive, at a packet parser, a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics;

interface with a processing element to determine a current operational state of the processing element;

select a first queue from the plurality of queues based on the current operational state of the processing element; and

forward a number of packets from the selected first queue to the processing element,

wherein to select the first queue from the plurality of queues, the instructions cause the machine to:

determine a current priority associated with each queue of a set of queues of the plurality of queues; and

select the first queue as the one with a highest priority of the current priorities of the set of queues from the set of queues; and

decrease the current priority of a second queue in the set of queues when the current operational state indicates that the processing element is not currently active and unable to process packets stored in the second queue.

21. The non-transitory medium of claim 20 , further comprising instructions to:

attempt to identify a queue of the plurality of queues that corresponds to a particular packet;

allocate a new queue when the identification fails; and

store the particular packet in the new queue.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 043120 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT. Recorded Aug 11, 2017
From: BIEDERMAN, DAN; ORR, MICHAEL
To: INTEL CORPORATION
Reel/Frame 043531/0073 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: BIEDERMAN, DAN; ORR, MICHAEL
To: INTEL COPRORATION
Reel/Frame 043120/0244 →
Continuity (1)
Related Publication 20180191642A1 · Jul 5, 2018
Cited By (5)
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