IP Library Granted Patent US 9,888,197
Granted Patent B1
US 9,888,197 · App. 15/398,137 · Granted Feb 6, 2018

Methods and apparatus for a CMOS image sensor with an in-pixel amplifier

Inventors: Jaroslav Hynecek (Allen, TX); Jeffery Steven Beck (Philomath, OR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/37457H01L27/1464H01L27/14621H01L27/14627H01L27/14634H01L27/14641H01L27/14645H04N5/3532H04N5/378
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Quick Facts
Patent No.
US 9,888,197
App. No.
15/398,137
Granted
Feb 6, 2018
Kind
B1
Abstract

Various embodiments of the present technology may comprise a method and apparatus for an image sensor. The image sensor may be configured as a stacked image sensor with two or more chips stacked vertically. The image sensor may comprise a plurality of pixel circuits, wherein portions of the pixel circuit are arranged on separate chips. Each pixel circuit may comprise an amplifier with a first feedback network to increase the sensor sensitivity, to reduce noise in the pixel signal, and to reduce the voltage swing on the FD node. Each pixel circuit may further comprise a second feedback network to stabilize the common-mode voltage of the pixel signal amplifier.

Claims (86)

1. An image sensor, comprising:

an array of photodetectors configured to generate charge in response to light; wherein

the charge is selectively transferred to a floating diffusion node;

a first amplifier coupled to a pixel output node and a feedback node and responsive to the charge stored in the floating diffusion node and configured to produce a pixel signal at the pixel output node,

wherein the first amplifier has a gain greater than unity;

a first row select device coupled between the drain terminal of the first amplifier and the pixel output node and responsive to a first signal;

a first feedback network adapted to selectively couple the pixel output node to the floating diffusion node; and

a second feedback network adapted to selectively couple the pixel output node to the feedback node.

2. The image sensor according to claim 1 , wherein the first feedback network comprises:

a first capacitor; and

a second row select device coupled to the first capacitor, wherein the second row select device is responsive to the first signal and selectively couples the pixel output node to the floating diffusion node.

3. The image sensor according to claim 1 , further comprising a second row select device responsive to a second signal to selectively couple the pixel output node to the floating diffusion node.

4. The image sensor according to claim 1 , further comprising a reset transistor coupled to a voltage source and the floating diffusion node, and responsive to a reset signal to remove charge from the floating diffusion node.

5. The image sensor according to claim 1 , further comprising:

a current source coupled to the feedback node, wherein the current source is configured to set a voltage level of the feedback node; and

a bias current coupled to the pixel output node, wherein the bias current is configured to load the first amplifier.

6. The image sensor according to claim 1 , further comprising a first transfer gate responsive to a second signal and coupled to at least one of the photodetectors, wherein the first transfer gate is configured to transfer charge to the floating diffusion node.

7. The image sensor according to claim 1 , wherein the second feedback network comprises:

a second amplifier responsive to a voltage potential at the pixel output node and coupled to the feedback node; and

a second capacitor coupled between the feedback node and the pixel output node.

8. The image sensor according to claim 1 , wherein the image sensor is configured as a backside illuminated image sensor.

9. The image sensor according to claim 1 , wherein the image sensor is configured as a stacked image sensor comprising:

a first chip, wherein the first chip comprises the array of photodetectors;

as second chip, wherein the second chip comprises the first feedback network;

a third chip, wherein the third chip comprises the second feedback network;

wherein:

the first chip and second chip are bonded together with a hybrid bond; and

the second chip and third chip are bonded together with a fusion bond.

10. A method for forming an image sensor, comprising:

forming an array of photodetectors;

forming a first circuit comprising:

a floating diffusion region coupled to at least one photodetector;

a first amplifier with a gain greater than unity;

a pixel output node;

a first feedback circuit;

wherein:

the feedback circuit couples the pixel output node to the floating diffusion region; and

the first circuit is coupled to a feedback node; and

forming a second circuit, coupled to the first circuit at the pixel output node and the feedback node, comprising:

a second feedback circuit, comprising a second amplifier, wherein the second feedback circuit is adapted to selectively couple the pixel output node to the feedback node.

11. The method for forming an image sensor according to claim 10 , further comprising:

coupling a current source to the feedback node; and

coupling a bias current to the pixel output node.

12. The method for forming an image sensor according to claim 10 , further comprising

forming a first chip wherein:

the first chip comprises the array of phototdetectors; and

the array of photodetectors form a backside illuminated sensor.

13. The method for forming an image sensor according to claim 12 , further comprising

forming a second chip, wherein the second chip comprises the first circuit; and

forming a third chip, wherein the third chip comprises the second circuit.

14. The method for forming an image sensor according to claim 13 , further comprising

forming a stacked image sensor with the first, second, and third chips by bonding a major surface of the first chip to a first major surface of the second chip, and bonding a second major surface of the second chip to a major surface of the third chip.

15. The method for forming an image sensor according to claim 14 , wherein:

bonding the first chip to the second chip comprises hybrid bonding; and

bonding the second chip to the third chip comprises fusion bonding.

16. An imaging system, comprising:

an image sensor, comprising:

a first chip, comprising:

an array of photodetectors; and

a first transfer gate responsive to a first signal and coupled to at least one photodetector, wherein the first transfer gate is configured to transfer charge out of the photodetector;

a second chip coupled to the first chip, comprising:

a charge storage node coupled to one or more photodetectors and configured to store charge generated by one of the photodetectors; and

a first amplifier responsive to the charge at the charge storage node, and configured to produce a pixel signal at a pixel output node, comprising:

a first terminal coupled to the first transfer gate;

a second terminal coupled to the pixel output node;

a third terminal coupled to a feedback node; and

wherein the first amplifier has a gain greater than unity;

a first row select device coupled between the second terminal of the first amplifier and the pixel output node and responsive to a second signal; and

a first feedback network coupled between the pixel output node and the charge storage node, comprising:

a first capacitor coupled between the pixel output node and the first terminal of the first amplifier; and

a second row select device coupled between the pixel output node and the first terminal of the first amplifier and responsive to the second signal; and

a third chip coupled to at least the second chip, comprising:

a third transfer gate responsive to a third signal and coupled between the second amplifier and the pixel output node; and

a second feedback network coupled between third transfer gate and the feedback node, comprising:

a second amplifier comprising:

a first terminal coupled to the feedback node;

a second terminal coupled to the third transfer gate; and

a second capacitor coupled between the feedback node and the second terminal of the second amplifier.

17. The imaging system according to claim 16 , wherein the second chip further comprises a reset transistor coupled to a voltage source and the charge storage region, and responsive to a reset signal to remove charge from the charge storage node.

18. The imaging system according to claim 16 , further comprising a current source coupled to the feedback node and a bias current coupled to the pixel output node.

19. The imaging system according to claim 16 , wherein:

the first chip and second chip are bonded together with hybrid bonds; and

the second chip and third chip are bonded together with a fusion bond.

20. The imaging system according to claim 16 , wherein:

the image sensor is configured as a backside illuminated image sensor; and

the first, second, and third chips are stacked vertically.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2017
From: HYNECEK, JAROSLAV; BECK, JEFFERY STEVEN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 040841/0052 →