IP Library Granted Patent US 11,238,131
Granted Patent B2
US 11,238,131 · App. 15/399,461 · Granted Feb 1, 2022

Sampling from an analog processor

Inventors: Firas Hamze (Vancouver, CA); James King (Vancouver, CA); Evgeny Andriyash (Vancouver, CA); Catherine McGeoch (Amherst, MA); Jack Raymond (Vancouver, CA); Jason Rolfe (Vancouver, CA); William G. Macready (West Vancouver, CA); Aaron Lott (Fremont, CA); Murray C. Thom (Vancouver, CA)
Assignee: D-WAVE SYSTEMS INC.
G06F17/18G06N10/00G06N20/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,238,131
App. No.
15/399,461
Granted
Feb 1, 2022
Kind
B2
Abstract

The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor, and reading out states for the qubits. The states for the qubits in the plurality of qubits correspond to a sample from the probability distribution. Operation of the sampling device may be summarized as including updating a set of samples to include the sample from the probability distribution, and returning the set of samples.

Claims (69)

1. A computational system comprising:

at least one analog processor comprising:

a plurality of qubits;

a plurality of coupling devices, wherein each coupling device provides controllable communicative coupling between a respective pair of the plurality of qubits;

at least one processor-based device communicatively coupled to the at least one analog processor; and

at least one non-transitory computer-readable storage medium that stores processor-executable instructions, which when executed causes at least one processor-based device to:

receive a sample from a function implemented on the at least one analog processor;

run a simulated annealing according to a backwards annealing schedule, the backwards annealing schedule comprising a starting condition, at least one intermediate condition, and a stopping condition, the backwards annealing schedule comprising a variable that defines a reverse annealing evolution and a rule for incrementing the variable along a series between the starting condition and the stopping condition and including the at least one intermediate condition, wherein the simulated annealing starts at the sample and generates a history of states of the simulated annealing as the variable is incremented, the history of states comprising at least one state corresponding to the intermediate condition of the backwards annealing schedule; and

return the history of states of the simulated annealing.

2. The computational system of claim 1 further comprising a readout subsystem responsive to a state of each of the qubits in the plurality of qubits to generate a first sample.

3. The computational system of claim 1 wherein, when executed, the processor-executable instructions further cause the at least one processor-based device to:

provide the backwards annealing schedule, the sample, and the function to a simulated annealer to run the simulated annealing.

4. The computational system of claim 3 wherein the backwards annealing schedule is an accelerated backwards annealing schedule.

5. The computational system of claim 3 wherein, when executed, the processor-executable instructions further cause the at least one processor-based device to:

record the history of states of the simulated annealing.

6. The computational system of claim 1 wherein, when executed, the processor-executable instructions cause the at least one processor-based device to:

compute a weight for the sample from the history of states of the simulated annealing.

7. The computational system of claim 6 wherein, when executed, the processor-executable instructions further cause the at least one processor-based device to:

compute the weight as proportional to a product over a plurality of states in the history of states of the simulated annealing, each term of the product includes an exponent of a multiplication of: a difference between an inverse temperature at a first state in the history of states of the simulated annealing and an inverse temperature at a second state in the history of states of the simulated annealing, and an energy at the second state in the history of states of the simulated annealing.

8. The computational system of claim 6 wherein, when executed, the processor-executable instructions further cause the at least one processor-based device to:

apply the weight to the sample in importance sampling.

9. The computational system of claim 6 wherein, when executed, the processor-executable instructions further cause the at least one processor-based device to:

record the weight.

10. The computational system of claim 6 wherein, when executed, the processor-executable instructions further cause the at least one processor-based device to:

return the weight.

11. The computational system of claim 1 wherein the starting condition, the at least one intermediate condition, and the stopping condition comprise an initial temperature, at least one intermediate temperature, and a final temperature, respectively.

12. A method of operation in a sampling device that comprises both an analog processor and at least one processor-based device communicatively coupled to one another, the analog processor comprising a plurality of qubits, and a plurality of coupling devices, wherein each coupling device provides controllable communicative coupling between a respective pair of the plurality of qubits, the method comprising:

receiving a sample from a function implemented on the analog processor;

running a simulated annealing in accordance with a backwards annealing schedule, the backwards annealing schedule comprising a starting condition, at least one intermediate condition, and a stopping condition, the backwards annealing schedule comprising a variable that defines a reverse annealing evolution and a rule for incrementing the variable along a series between the starting condition and the stopping condition and including the at least one intermediate condition, wherein the simulated annealing starts at the sample and generates a history of states of the simulated annealing as the variable is incremented, the history of states comprising at least one state corresponding to the intermediate condition of the backwards annealing schedule; and

returning the history of states of the simulated annealing.

13. The method of claim 12 further comprising:

providing the backwards annealing schedule, the sample, and the function to a simulated annealer to run the simulated annealing.

14. The method of claim 13 further comprising:

including an accelerated backwards annealing schedule in the backwards annealing schedule.

15. The method of claim 12 further comprising:

computing a weight for the sample from the history of states of the simulated annealing.

16. The method of claim 15 further comprising:

computing the weight as proportional to a product over a plurality of states in the history of states of the simulated annealing, each term of the product includes an exponent of a multiplication of: a difference between an inverse temperature at a first state in the history of states of the simulated annealing and an inverse temperature at a second state in the history of states of the simulated annealing, and an energy at the second state in the history of states of the simulated annealing.

17. The method of claim 15 further comprising:

applying the weight to the sample in importance sampling.

18. The method of claim 15 further comprising:

recording the weight.

19. The method of claim 15 further comprising:

returning the weight.

20. The method of claim 15 further comprising:

recording the history of states of the simulated annealing.

21. The method of claim 12 wherein receiving the sample from the function implemented on an analog processor further comprises:

fixing a first qubit in the plurality of qubits to a known state.

22. The method of claim 12 wherein running a simulated annealing in accordance with a backwards annealing schedule, the backwards annealing schedule comprising a starting condition, at least one intermediate condition, and a stopping condition comprises running a simulated annealing in accordance with a backwards annealing schedule, the backwards annealing schedule comprising an initial temperature, at least one intermediate temperature, and a final temperature, respectively.

23. A non-transitory computer-readable storage medium that stores processor-executable instructions, which when executed cause at least one processor to:

receive a sample from a function implemented on an analog processor;

run a simulated annealing according to a backwards annealing schedule, the backwards annealing schedule comprising a starting condition, at least one intermediate condition, and a stopping condition, the backwards annealing schedule comprising a variable that defines a reverse annealing evolution and a rule for incrementing the variable along a series between the starting condition and the stopping condition and including the at least one intermediate condition, wherein the simulated annealing starts at the sample and generates a history of states of the simulated annealing as the variable is incremented, the history of states comprising at least one state corresponding to the intermediate condition of the backwards annealing schedule; and

return the history of states of the simulated annealing.

24. The computer-readable storage medium of claim 23 wherein the processor-executable instructions when executed further cause the at least one processor to:

provide the backwards annealing schedule, the sample, and the function to a simulated annealer to run the simulated annealing.

25. The computer-readable storage medium of claim 24 wherein the backwards annealing schedule is an accelerated backwards annealing schedule.

26. The computer-readable storage medium of claim 24 wherein the processor-executable instructions when executed further cause the at least one processor to run backwards simulated annealing on the sample includes instruction to:

record the history of states of the simulated annealing.

27. The computer-readable storage medium of claim 23 wherein the processor-executable instructions when executed further cause the at least one processor to:

compute a weight for the sample from the history of states of the simulated annealing.

28. The computer-readable storage medium of claim 27 wherein the processor-executable instructions when executed further cause the at least one processor to compute a weight for the sample from the history of states of the simulated annealing includes instructions to:

compute the weight as proportional to a product over a plurality of states in the history of states of the simulated annealing, each term of the product includes an exponent of a multiplication of: a difference between an inverse temperature at a first state in the history of states of the simulated annealing and an inverse temperature at a second state in the history of states of the simulated annealing, and an energy at the second state in the history of states of the simulated annealing.

29. The computer-readable storage medium of claim 27 wherein the processor-executable instructions when executed further cause the at least one processor to:

apply the weight to the sample in importance sampling.

30. The computer-readable storage medium of claim 27 wherein the processor-executable instructions when executed further cause the at least one processor to:

record the weight.

31. The computer-readable storage medium of claim 27 wherein the processor-executable instructions when executed further cause the at least one processor to:

return the weight.

32. The computer-readable storage medium of claim 23 wherein the starting condition, the at least one intermediate condition, and the stopping condition comprise an initial temperature, at least one intermediate temperature, and a final temperature, respectively.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
RELEASE OF SECURITY INTEREST Recorded Sep 20, 2022
From: PSPIB UNITAS INVESTMENTS II INC., IN ITS CAPACITY AS COLLATERAL AGENT
To: D-WAVE SYSTEMS INC.
Reel/Frame 061493/0694 →
SECURITY INTEREST Recorded Mar 3, 2022
From: D-WAVE SYSTEMS INC.
To: PSPIB UNITAS INVESTMENTS II INC.
Reel/Frame 059317/0871 →
CORRECTIVE ASSIGNMENT TO CORRECT THE COMMA REMOVE OUT OF CONVEYING AND RECEIVING PARTIES NAMES PREVIOUSLY RECORDED AT REEL: 57291 FRAME: 095. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 5, 2021
From: D-WAVE SYSTEMS INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 057770/0314 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE THE COMMA FROM THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 057194 FRAME: 0669. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 5, 2021
From: DWSI HOLDINGS INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 057718/0700 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 57056 FRAME: 531. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 5, 2021
From: HAMZE, FIRAZ; KING, JAMES; ANDRIYASH, EVGENY; RAYMOND, JACK; ROLFE, JASON; MACREADY, WILLIAM G.; LOTT, AARON; THOM, MURRAY C.; MCGEOCH, CATHERINE; D-WAVE (COMMERCIAL) INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 057762/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 057656 FRAME 0015. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 5, 2021
From: D-WAVE SYSTEMS INC.; DWSI HOLDINGS INC.
To: DWSI HOLDINGS INC.
Reel/Frame 058272/0110 →
MERGER AND CHANGE OF NAME Recorded Aug 30, 2021
From: D-WAVE SYSTEMS, INC.; DWSI HOLDINGS INC.; DWSI HOLDINGS INC.
To: DWSI HOLDINGS INC.
Reel/Frame 057656/0015 →
CONTINUATION Recorded Aug 16, 2021
From: D-WAVE SYSTEMS, INC.
To: D-WAVE SYSTEMS, INC.
Reel/Frame 057291/0095 →
CHANGE OF NAME Recorded Aug 16, 2021
From: DWSI HOLDINGS INC.
To: D-WAVE SYSTEMS, INC.
Reel/Frame 057194/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2021
From: HAMZE, FIRAS; KING, JAMES; ANDRIYASH, EVGENY; RAYMOND, JACK; ROLFE, JASON; MACREADY, WILLIAM G.; LOTT, AARON; THOM, MURRAY C.; MCGEOCH, CATHERINE; D-WAVE (COMMERCIAL) INC.
To: D-WAVE SYSTEMS, INC.
Reel/Frame 057056/0531 →