Methods and apparatus for an analog-to-digital converter

1. An analog-to-digital converter capable of receiving a first signal and a ramp signal, comprising:

a generator circuit configured to generate a second signal based on a predetermined time interval;

a compare circuit coupled to the generator circuit and configured to:

compare the ramp signal to at least one of the first signal and the second signal; and

generate an output based on the relationship between the ramp signal and at least one of the first signal and the second signal; and

a conversion circuit coupled to the compare circuit and configured to generate a digital output signal based on the first signal;

wherein the predetermined time interval is the time between a change in the compare circuit output and an immediately following strobe signal.

2. The analog-to-digital converter according to claim 1 , wherein the generator circuit comprises:

a current source;

a switch coupled to the current source and responsive to the compare circuit output; and

a capacitor selectively coupled to the current source via the switch, wherein the capacitor charges during the predetermined time interval to generate the second signal.

3. The analog-to-digital converter according to claim 1 , wherein the conversion circuit comprises:

a counter circuit, coupled to a current source and a clock signal, and configured to produce a plurality of binary numbers; and

a first storage device coupled to the counter circuit to receive the binary numbers and responsive to the compare circuit output, wherein the first storage device transmits one of the binary numbers according to the compare circuit output, and wherein the transmitted binary number represents a plurality of least-significant bits of the first signal.

4. The analog-to-digital converter according to claim 3 , further comprising a second storage device coupled to the counter circuit to receive the binary numbers and responsive to the compare circuit output, wherein the second storage device transmits one of the binary numbers according to the compare circuit output, and wherein the transmitted binary number represents a plurality of most-significant bits of the first signal.

5. The analog-to-digital converter according to claim 4 , further comprising a logic unit coupled to the first and second storage devices and configured to convert the least-significant bits and the most-significant bits to a corresponding ADC output value.

6. The analog-to-digital converter according to claim 1 , further comprising a synchronization circuit coupled to:

a strobe signal;

at least one of a calibration signal and the compare circuit output; and

the conversion circuit; and

wherein the synchronization circuit is responsive to each of the calibration signal and the compare circuit, and the synchronization circuit transmits a signal to the conversion circuit according to the strobe signal.

7. The analog-to-digital converter according to claim 1 , wherein the second signal is generated during a coarse conversion phase, and the compare circuit compares the second signal to the ramp signal during a fine conversion phase.

8. The analog-to-digital converter according to claim 1 , further comprising a reset circuit responsive to a reset signal, and selectively coupled to the generator circuit during a calibration phase.

9. A method for converting an analog signal into a digital signal, comprising:

generating a ramp signal;

comparing the analog signal to the ramp signal;

generating a time-residue signal during a coarse conversion phase, wherein the time-residue signal corresponds to a voltage that is proportional to a first predetermined time interval;

comparing the time-residue signal to the ramp signal;

determining a plurality of most-significant bits of the digital signal during the coarse conversion phase; and

determining a plurality of least-significant bits of the digital signal during a fine conversion phase according to the voltage generated during the coarse conversion phase.

10. The method for converting an analog signal into a digital signal according to claim 9 , further comprising scaling the least-significant bits according to a calibration factor.

11. The method for converting an analog signal into a digital signal according to claim 9 , further comprising calibrating the least-significant bits, wherein calibrating comprises:

determining a first value during a calibration phase;

determining a second value during the calibration phase;

determining a magnitude change from the first value to the second value; and

dividing the least-significant bits by the magnitude change.

12. The method for converting an analog signal into a digital signal according to claim 11 , wherein:

determining the first value during the calibration phase comprises charging a capacitor for a second predetermined time interval; and

determining the second value during the calibration phase comprises charging the capacitor for a third predetermined time interval greater than the second predetermined time interval.

13. The method for converting an analog signal into a digital signal according to claim 9 , wherein the ramp signal comprises a smooth ramp waveform.

14. An analog-to-digital converter capable of receiving a first signal and a ramp signal, comprising:

a comparator coupled to the first signal and the ramp signal, and configured to:

compare the ramp signal to at least the first signal and a second signal; and

generate an output based on the relationship between the ramp signal and at least one of the first signal and the second signal; and

a generator circuit responsive to the comparator output, comprising:

a current source; and

a capacitor selectively coupled to the current source, wherein the current source charges the capacitor for a predetermined time interval to generate the second signal;

a conversion circuit coupled to the comparator and configured to generate a digital output signal based on the first signal, comprising:

a counter circuit coupled to the current source and a clock signal and configured to produce a plurality of binary numbers; and

a first storage device coupled to the counter circuit to receive the binary numbers and responsive to the comparator output, wherein the first storage device transmits a first binary number according to the comparator output, and wherein the first binary number represents a plurality of least-significant bits of the first signal; and

a second storage device coupled to the counter circuit to receive the binary numbers and responsive to the comparator output, wherein the second storage device transmits a second binary number according to the comparator output, and wherein the second binary number represents a plurality of most-significant bits of the first signal.

15. The analog-to-digital converter according to claim 14 , further comprising a logic unit coupled to the first and second storage devices and configured to convert the least-significant bits and the most-significant bits to a corresponding ADC output value.

16. The analog-to-digital converter according to claim 14 , further comprising a synchronization circuit coupled to:

a strobe signal;

at least one of a calibration signal and the comparator output; and

the conversion circuit; and

wherein the synchronization circuit is responsive to each of the calibration signal and the comparator, and the synchronization circuit transmits a signal to the conversion circuit according to the strobe signal.

17. The analog-to-digital converter according to claim 14 , wherein the predetermined time interval is the time between a change in the comparator output and an immediately following strobe signal.

18. The analog-to-digital converter according to claim 14 , wherein the second signal is generated during a coarse conversion phase, and the comparator compares the second signal to the ramp signal during a fine conversion phase.

19. The analog-to-digital converter according to claim 14 , further comprising a reset circuit responsive to a reset signal, and wherein the reset circuit selectively couples to the generator circuit during a calibration phase.