IP Library Patent Application 15408323
Patent Application
App. No. 15/408,323

METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE

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Quick Facts
Patent No.
US None
App. No.
15/408,323
Abstract

A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and using a distributed flag architecture to emulate a centralized flag architecture for the emulation of guest instruction execution.

Claims (27)

1 . A method for emulating a guest centralized flag architecture by using a native distributed flag architecture, comprising:

grouping an incoming instruction sequence to form instruction blocks, wherein each of the instruction blocks comprise two half blocks;

scheduling the instructions of the instruction block to execute in accordance with a scheduler; and

using a distributed flag architecture to emulate a centralized guest flag architecture for the emulation of guest instruction execution.

2 . The method of claim 1 , wherein the incoming instruction sequence is received using a global front end and wherein each half block is operable to be dispatched independently.

3 . The method of claim 1 , wherein a distributed flag architecture is configured to be implemented using multiple independent flag registers.

4 . The method of claim 1 , wherein, guest instructions are categorized into 4 native instruction types.

5 . The method of claim 1 , wherein guest instructions are categorized into 4 native instruction types and guest instruction types update different guest instruction flags, based on their type.

6 . The method of claim 1 , wherein a front end dynamic converter categorizes incoming instructions based on the manner in which they update guest instruction flags.

7 . A non-transitory computer readable media having computer readable code which when executed by a computer system causes the computer system to perform a method for emulating a guest centralized flag architecture by using a native distributed flag architecture, comprising:

grouping an incoming instruction sequence to form instruction blocks, wherein each of the instruction blocks comprise two half blocks;

scheduling the instructions of the instruction block to execute in accordance with a scheduler; and

using a distributed flag architecture to emulate a centralized guest flag architecture for the emulation of guest instruction execution.

8 . The computer readable media of claim 7 , wherein the incoming instruction sequence is received using a global front end and wherein each half block is operable to be dispatched independently.

9 . The computer readable media of claim 7 , wherein a distributed flag architecture is configured to be implemented by using multiple independent flag registers.

10 . The computer readable media of claim 7 , wherein, guest instructions are categorized into 4 native instruction types.

11 . The computer readable media of claim 7 , wherein guest instructions are categorized into 4 native instruction types and guest instruction types update different guest instruction flags, based on their type.

12 . The computer readable media of claim 7 , wherein a front end/dynamic converter categorizes incoming instructions based on the manner in which they update guest instruction flags.

13 . A computer system having a processor coupled to a memory, the memory having computer readable code which when executed by the computer system causes the computer system to implement a method for emulating a guest centralized flag architecture by using a native distributed flag architecture, comprising:

grouping an incoming instruction sequence to form instruction blocks, wherein each of the instruction blocks comprise two half blocks;

scheduling the instructions of the instruction block to execute in accordance with a scheduler; and

using a distributed flag architecture to emulate a centralized guest flag architecture for the emulation of guest instruction execution.

14 . The computer system of claim 13 , wherein the incoming instruction sequence is received using a global front end and wherein each half block is operable to be dispatched independently.

15 . The computer system of claim 13 , wherein a distributed flag architecture is configured to be implemented by using multiple independent flag registers.

16 . The computer system of claim 13 , wherein, guest instructions are categorized into 4 native instruction types.

17 . The computer system of claim 13 , wherein guest instructions are categorized into 4 native instruction types and guest instruction types update different guest instruction flags, based on their type.

18 . The computer system of claim 13 , wherein a front end/dynamic converter categorizes incoming instructions based on the manner in which they update guest instruction flags.