Semiconductor packages with an intermetallic layer
View Patent ↗A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.
1. A semiconductor package, comprising:
a die coupled to a first sublayer, the first sublayer deposited directly onto a second sublayer, wherein the first sublayer and the second sublayer each comprise a metal selected from a group consisting of titanium, copper, chromium, and any combination thereof;
an intermetallic layer deposited directly onto the second sublayer where the intermetallic layer reflows a second time only at a temperature greater than a temperature applied when the intermetallic layer was first reflowed; and
a substrate comprising only a silver layer deposited directly onto the substrate, the silver layer deposited directly onto the intermetallic layer;
wherein the intermetallic layer comprises a plurality of sublayers; and
wherein the intermetallic layer is not a solder.
2. The package of claim 1 , wherein the first sublayer comprises titanium.
3. The package of claim 1 , wherein the intermediate layer further comprised a copper layer before the intermetallic layer was reflowed.
4. The package of claim 1 , wherein the intermediate layer further comprised a silver layer before the intermetallic layer was reflowed.
5. The package of claim 1 , wherein the intermediate layer further comprised both a copper layer and a silver layer before the intermetallic layer was reflowed.
6. The package of claim 1 , wherein the semiconductor package is formed using one of no solder paste and no solder preform.