Semiconductor memory device and memory system
View Patent ↗A semiconductor memory device includes a plurality of memory cells, a plurality of word lines, including a word line that is connected to a group of the memory cells, and a control circuit configured to execute a write operation on the memory cells of the group. The write operation includes multiple program loops including a first program loop and a second program loop that is executed at a later time than the first program loop, and for each subsequent program loop, a program voltage that is applied to the first word line is increased from that of a current program loop. The program voltage is increased by a first amount from that of the current program loop if the next program loop is the first program loop and by a second amount that is less than the first amount if the next program loop is the second program loop.
1. A semiconductor memory device comprising:
a plurality of memory cells;
a plurality of word lines, including a first word line connected to a group of the memory cells and other word lines connected to the memory cells that are not in the group; and
a control circuit configured to execute a write operation on the memory cells of the group, wherein
the write operation includes multiple program loops including a first program loop, and a second program loop that is executed at a later time than the first program loop, and
each multiple program loop includes a verify operation during which threshold voltages of the memory cells of the group are verified, and a program operation and a detection operation that are carried out in parallel, wherein a program voltage is applied to the first word line during the program operation and pass results of the verify operation are confirmed during the detection operation, the program voltage for a subsequent loop being determined based on the detection operation and increased by a first amount from that of a current program loop if the next program loop is the first program loop and by a second amount that is less than the first amount if the next program loop is the second program loop.
2. The device according to claim 1 , wherein
the multiple program loops further include a third program loop that is executed at a later time than the second program loop, and
the program voltage is increased by a third amount that is less than the second amount from that of the current program loop if the next program loop is the third program loop.
3. The device according to claim 1 , wherein an amount of increase in the program voltage for the subsequent program loop from that of the current program loop is reduced according to a number of program loops that have been executed.
4. The device according to claim 1 , wherein an amount of increase in the program voltage for the subsequent program loop from that of the current program loop is reduced if the program voltage for the current program loop is less than a threshold program voltage.
5. The device according to claim 1 , wherein
during the write operation on the memory cells of the group, a write pass voltage, which is less than the program voltage and greater than a ground voltage, is applied to the other word lines, and for each subsequent program loop, the write pass voltage is increased from that of the current program loop, and
the write pass voltage is increased by a third amount from that of the current program loop if the next program loop is the first program loop and by a fourth amount that is less than the third amount if the next program loop is the second program loop.
6. The device according to claim 1 , wherein one of three different verify voltages are applied to the first word line during the verify operation.
7. The device according to claim 1 , wherein write one of seven different verify voltages are applied to the first word line during the verify operation.
8. The device according to claim 1 , wherein one of fifteen different verify voltages are applied to the first word line during the verify operation.
9. The device according to claim 1 , wherein the memory cells are arranged in two-dimensions.
10. The device according to claim 1 , wherein the memory cells are arranged in three-dimensions.
11. A method of performing a write operation in multiple program loops in a semiconductor memory device including a plurality of memory cells, and a plurality of word lines including a first word line connected to a group of the memory cells and other word lines connected to the memory cells that are not in the group, said method comprising:
(a) executing a first program operation on the memory cells in the group by applying a program voltage to the first word line;
(b) executing a verify operation to determine threshold voltage levels of the memory cells in the group;
(c) executing a second program operation and a detection operation in parallel, wherein an increased program voltage is applied to the first word line during the second program operation and pass results of the verify operation are confirmed during the detection operation; and
repeating steps (b) and (c) until each of the memory cells in the group has reached a target threshold voltage thereof,
wherein one program loop includes steps (b) and (c), and the program voltage for a subsequent program loop is determined based on the detection operation and increased by a first amount from that of a current program loop if the next program loop is a first program loop and by a second amount that is less than the first amount if the next program loop is a second program loop which is executed at a later time than the first program loop.
12. The method of claim 11 , wherein
the program voltage for the subsequent program loop is increased by a third amount that is less than the second amount from that of the current program loop if the next program loop is a third program loop which is executed at a later time than the second program loop.
13. The method of claim 11 , wherein an amount of increase in the program voltage is reduced according to a number of program loops that have been executed.
14. The method of claim 11 , wherein an amount of increase in the program voltage is reduced if the program voltage for the current program loop is less than a threshold program voltage.
15. The method of claim 11 , wherein
during each program operation, applying a write pass voltage, which is less than the program voltage and greater than a ground voltage, to the other word lines, and for each subsequent program loop, the write pass voltage is increased from that of the current program loop, and
the write pass voltage is increased by a third amount from that of the current program loop if the next program loop is the first program loop and by a fourth amount that is less than the third amount if the next program loop is the second program loop.
16. The method of claim 11 , wherein one of three different verify voltages are applied to the first word line during the verify operation.
17. The method of claim 11 , wherein one of seven different verify voltages are applied to the first word line during the verify operation.
18. The method of claim 11 , wherein one of fifteen different verify voltages are applied to the first word line during the verify operation.