Window based mapping

1. A flash memory device comprising:

a flash memory;

a volatile memory configured to store a first logical address to physical address (L2P) map and a second L2P map, wherein a unit of data pointed to by the first L2P map is smaller than a unit of data pointed to by the second L2P map, and wherein a total map size in the volatile memory is based on a size of the first L2P map and a size of the second L2P map in the volatile memory; and

a controller configured to:

receive an access request with a logical address for access to data on the flash memory;

compare the logical address of the access request with a plurality of windows of a window table, wherein each window is a contiguous range of logical addresses between a start address and an end address, and wherein the size of the first L2P map in the volatile memory is based on a number of windows and a size of a respective window in the plurality of windows;

determine whether the logical address of the access request is located between a first start address and a first end address associated with at least one of the plurality of windows of the window table; and

upon determining that the logical address of the access request is located between the first start address and the first end address associated with the at least one window of the plurality of windows, use the first L2P map stored in the volatile memory to address to a physical address associated with the flash memory, wherein an ordering of physical addresses addressed to by the first L2P map differs from an ordering of corresponding logical addresses in the first L2P map.

2. The flash memory device of claim 1 , wherein upon determining that the logical address of the access request is not located between a respective start address and a respective end address associated with any of the plurality of windows, the controller is further configured to use the second L2P map stored in the volatile memory to translate the logical address to the physical address associated with the flash memory.

3. The flash memory device of claim 1 , wherein the window table comprising the plurality of windows is stored on a different volatile memory with an access time shorter than the access time for the volatile memory storing the first L2P map and the second L2P map.

4. The flash memory device of claim 1 , wherein:

the window table comprising the plurality of windows is stored in tightly coupled memory (TCM) on the controller; and

determining whether the logical address is located between the first start address and the first end address comprises reading at least the first start address and the first end address from the TCM.

5. The flash memory device of claim 1 , wherein the plurality of windows include windows with variable sizes.

6. The flash memory device of claim 1 , wherein the flash memory comprises a plurality of flash memory blocks, wherein the first L2P map corresponds to a first set of flash memory blocks and the second L2P map corresponds to a second set of flash memory blocks from the plurality of flash memory blocks.

7. The flash memory device of claim 1 , wherein the data associated with the first L2P map includes data that is accessed a number of times within a predetermined time period and wherein the number of times is greater than a threshold.

8. The flash memory device of claim 1 , wherein the data associated with the second L2P map includes data that is accessed a number of times within a predetermined time period and wherein the number of times is smaller than a threshold.

9. The flash memory device of claim 1 , wherein the first L2P map represents a window of a certain contiguous range of logical addresses corresponding to an implied map associated with the second L2P map, wherein the implied map points to a unit of data equal to the unit of data pointed to by the first L2P map.

10. The flash memory device of claim 1 , wherein the controller is further configured to move the at least one window in the plurality of windows;

moving the at least one window involves changing a corresponding start address in the window table to a second start address different from the first start address and/or changing a corresponding end address in the window table to a second end address different from the first end address, during run time based on a frequency of data accesses of addresses within the windows; and

a second lookup in the window table for a second logical address between the first start address and the first end address results in the second logical address not found.

11. The flash memory device of claim 1 , wherein the volatile memory is a dynamic random access memory (DRAM).

12. The flash memory device of claim 10 , wherein:

moving the at least one window during run time based on the frequency of data accesses of addresses further comprises moving the at least one window in response to a third logical address located between the first start address and the first end address being accessed less than a threshold frequency; and

the controller is further configured, responsive to the second logical address not being found in the window table during the second lookup, to use the second L2P map stored in the volatile memory to translate the second logical address to a second physical address associated with the flash memory.

13. The flash memory device of claim 10 , wherein, responsive to the at least one window being moved, the first L2P map is modified to map logical addresses between the second start address and the second end address to physical addresses.

14. A method comprising:

receiving, by a flash memory controller, an access request with a logical address for access to data on a flash memory, the flash memory communicatively coupled to the flash memory controller and to a volatile memory, wherein the volatile memory is configured to store a first logical address to physical address (L2P) map and a second L2P map, wherein a unit of data pointed to by the first L2P map is smaller than a unit of data pointed to by the second L2P map, and wherein a total map size in the volatile memory is based on a size of the first L2P map and a size of the second L2P map in the volatile memory;

comparing the logical address of the access request with a plurality of windows of a window table, wherein each window is a contiguous range of logical addresses between a start address and an end address, and wherein the size of the first L2P map in the volatile memory is based on a number of windows and a size of a respective window in the plurality of windows;

determining that the logical address of the access request is located between a first start address and a first end address associated with at least one of the plurality of windows of the window table; and

translating the logical address to a physical address associated with the flash memory using the first L2P map stored in the volatile memory, wherein an ordering of physical addresses addressed to by the first L2P map differs from an ordering of corresponding logical addresses in the first L2P map.

15. The method of claim 14 , wherein the second L2P map stored in the volatile memory is used to translate the logical address to the physical address associated with the flash memory if the logical address of the access request is not located between a respective start address and a respective end address associated with any of the plurality of windows.

16. The method of claim 14 , wherein the window table comprising the plurality of windows is stored in tightly coupled memory (TCM) on the flash memory controller; and

determining that the logical address is located within at least one of the plurality of windows comprises reading at least the first start address and the first end address from the TCM.

17. The method of claim 14 , wherein the access request includes a request to perform a read or a write of the flash memory at the logical address.

18. A non-transitory computer readable medium having stored thereon instructions that, when executed by a processor, perform a method, comprising:

receiving an access request with a logical address for access to data on a flash memory, the flash memory communicatively coupled to the processor and to a volatile memory, wherein the volatile memory is configured to store a first logical address to physical address (L2P) map and a second L2P map, wherein a unit of data pointed to by the first L2P map is smaller than a unit of data pointed to by the second L2P map, and wherein a total map size in the volatile memory is based on a size of the first L2P map and a size of the second L2P map in the volatile memory;

comparing the logical address of the access request with a plurality of windows of a window table, wherein each window is a contiguous range of logical addresses between a start address and an end address, and wherein the size of the first L2P map in the volatile memory is based on a number of windows and a size of a respective window in the plurality of windows;

determining that the logical address of the access request is located between a first start address and a first end address associated with at least one of the plurality of windows of the window table; and

translating the logical address to a physical address associated with the flash memory using the first L2P map stored in the volatile memory, wherein an ordering of physical addresses addressed to by the first L2P map differs from an ordering of corresponding logical addresses in the first L2P map.

19. The non-transitory computer readable medium of claim 18 , wherein the second L2P map stored in the volatile memory is used to translate the logical address to the physical address associated with the flash memory if the logical address of the access request is not located between a respective start address and a respective end address associated with any of the plurality of windows.

20. The non-transitory computer readable medium of claim 18 , wherein the processor is part of a flash memory controller.