Booster circuit

1. A booster circuit comprising:

a charge pump circuit including a plurality of transistors connected in series in each of which a gate and a channel electrode are connected, and a plurality of capacitors each of which is connected to the channel electrode of a corresponding one of the transistors; and

a clock processing circuit including

a first transistor of a first conductivity type and a second transistor of a second conductivity type that are connected in series between a high-voltage node and a low-voltage node, gates of the first and second transistors being connected to each other, and

a third transistor of the second conductivity type connected in parallel with the first transistor between the high-voltage node and a first output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to at least one of the capacitors of the charge pump circuit.

2. The booster circuit according to claim 1 , wherein

the clock processing circuit inputs a clock signal to the gates of the first and second transistors, and an inverted clock signal to a gate of the third transistor.

3. The booster circuit according to claim 2 , wherein

when the high-voltage terminal is at a voltage level not sufficient to turn on the first transistor, the third transistor is turned on.

4. The booster circuit according to claim 1 , wherein

the clock processing circuit inputs an inverted clock signal to the gates of the first and second transistors, and a clock signal to a gate of the third transistor.

5. The booster circuit according to claim 4 , wherein

when the high-voltage terminal is at a voltage level not sufficient to turn on the first transistor, the third transistor is turned on.

6. The booster circuit according to claim 1 , wherein

the clock processing circuit further includes a fourth transistor of the first conductivity type that is connected to the high-voltage node, and a voltage corresponding to the output voltage of the charge pump circuit is applied to a gate of the fourth transistor.

7. The booster circuit according to claim 6 , wherein the clock processing circuit further includes

a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type that are connected in series between the high-voltage node and the low-voltage node, gates of the fifth and sixth transistors being connected to each other, and

a seventh transistor of the second conductivity type connected in parallel with the fifth transistor between the high-voltage node and a second output terminal of the clock processing circuit that is connected to a node between the fifth transistor and the sixth transistor and to at least one of the capacitors of the charge pump circuit that is different from said at least one of the capacitors connected to the output terminal.

8. The booster circuit according to claim 7 , wherein

the clock processing circuit inputs a clock signal to gates of the first, second, and seventh transistors, and an inverted clock signal to gates of the third, fifth, and sixth transistors.

9. The booster circuit according to claim 7 , wherein

the clock processing circuit inputs an inverted clock signal to gates of the first, second, and seventh transistors, and a clock signal to gates of the third, fifth, and sixth transistors.

10. The booster circuit according to claim 7 , wherein

the clock processing circuit further includes a first inverter having an output terminal that is connected to the gates of the first and second transistors, and a second inverter having an output terminal that is connected to the gates of the fifth and sixth transistors and to an input terminal of the first inverter.

11. A semiconductor memory device comprising:

a semiconductor memory cell array; and

a peripheral circuit configured to control operation of the semiconductor memory cell array, the peripheral circuit including a booster circuit configured to generate voltages used for the operation, wherein

the booster circuit includes:

a charge pump circuit including a plurality of transistors connected in series in each of which a gate and a channel electrode are connected, and a plurality of capacitors each of which is connected to the channel electrode of a corresponding one of the transistors; and

a clock processing circuit including

a first transistor of a first conductivity type and a second transistor of a second conductivity type that are connected in series between a high-voltage node and a low-voltage node, gates of the first and second transistors being connected to each other, and

a third transistor of the second conductivity type connected in parallel with the first transistor between the high-voltage node and a first output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to at least one of the capacitors of the charge pump circuit.

12. The semiconductor memory device according to claim 11 , wherein

the clock processing circuit inputs a clock signal to the gates of the first and second transistors, and an inverted clock signal to a gate of the third transistor.

13. The semiconductor memory device according to claim 12 , wherein

when the high-voltage terminal is at a voltage level not sufficient to turn on the first transistor, the third transistor is turned on.

14. The semiconductor memory device according to claim 11 , wherein

the clock processing circuit inputs an inverted clock signal to the gates of the first and second transistors, and a clock signal to a gate of the third transistor.

15. The semiconductor memory device according to claim 14 , wherein

when the high-voltage terminal is at a voltage level not sufficient to turn on the first transistor, the third transistor is turned on.

16. The semiconductor memory device according to claim 11 , wherein

the clock processing circuit further includes a fourth transistor of the first conductivity type that is connected to the high-voltage node, and a voltage corresponding to the output voltage of the charge pump circuit is applied to a gate of the fourth transistor.

17. The semiconductor memory device according to claim 16 , wherein

the clock processing circuit further includes

a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type that are connected in series between the high-voltage node and the low-voltage node, gates of the fifth and sixth transistors being connected to each other, and

a seventh transistor of the second conductivity type connected in parallel with the fifth transistor between the high-voltage node and a second output terminal of the clock processing circuit that is connected to a node between the fifth transistor and the sixth transistor and to at least one of the capacitors of the charge pump circuit that is different from said at least one of the capacitors connected to the output terminal.

18. The semiconductor memory device according to claim 17 , wherein

the clock processing circuit inputs a clock signal to gates of the first, second, and seventh transistors, and an inverted clock signal to gates of the third, fifth, and sixth transistors.

19. The semiconductor memory device according to claim 17 , wherein

the clock processing circuit inputs an inverted clock signal to gates of the first, second, and seventh transistors, and a clock signal to gates of the third, fifth, and sixth transistors.

20. The semiconductor memory device according to claim 17 , wherein

the clock processing circuit further includes a first inverter having an output terminal that is connected to the gates of the first and second transistors, and a second inverter having an output terminal that is connected to the gates of the fifth and sixth transistors and to an input terminal of the first inverter.