Efficient data path architecture for flash devices configured to perform multi-pass programming
Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.
1. A flash memory device comprising:
a flash memory comprising:
a flash memory block comprising a plurality of pages, each page comprising a plurality of M-level cells, wherein each page of data is programmed into the flash memory in multiple passes by writing a same page of data to a respective page of the plurality of M-level cells of the flash memory for each of the multiple passes;
a flash memory controller configured to:
receive a request from a host system with data to be written into the flash memory; and
enable writing of the data into the flash memory in multiple passes for programming a given page;
a first volatile memory configured to store the data to be written into the flash memory for a first pass;
a second volatile memory configured to store the data to be written into the flash memory for subsequent passes after the first pass; and
a write path comprising:
an encoder channel configured to encode the data to be written into the flash memory for the first pass from the first volatile memory while bypassing the second volatile memory;
a write back channel configured to store the encoded data into the second volatile memory; and
a bypass channel configured to send the encoded data stored in the second volatile memory for writing into the flash memory for the subsequent passes.
2. The flash memory device of claim 1 , wherein the first volatile memory is on a same chip as the flash memory controller.
3. The flash memory device of claim 1 , wherein the second volatile memory is not on the same chip as the first volatile memory.
4. The flash memory device of claim 1 , wherein the first volatile memory is smaller in capacity than the second volatile memory.
5. The flash memory device of claim 1 , wherein the first volatile memory is a static random access memory (SRAM).
6. The flash memory device of claim 1 , wherein the second volatile memory is a dynamic random access memory (DRAM).
7. The flash memory device of claim 1 , wherein the M is 3 and the plurality of M-level cells include triple level cells (TLCs).
8. The flash memory device of claim 1 , wherein the encoder channel includes an error correction code (ECC) encoder.
9. The flash memory device of claim 1 , wherein the encoder channel includes a low density parity check (LDPC) encoder and the encoded data includes an LDPC parity.
10. The flash memory device of claim 1 , further comprising a buffer manager communicatively coupled to the first volatile memory and to the second volatile memory, wherein the buffer manager is configured to receive instructions from the flash memory controller for communicating with the first volatile memory and the second volatile memory.
11. A method comprising:
receiving, by a processor, a request from a host system with data to be written into a flash memory, wherein the data is stored in a first volatile memory, wherein the flash memory includes a flash memory block comprising a plurality of pages, each page comprising a plurality of M-level cells, wherein each page of data is programmed into the flash memory in multiple passes by writing a same page of data to a respective page of the plurality of M-level cells of the flash memory for each of the multiple passes;
communicating with a buffer manager, communicatively coupled to the processor, to read the data stored in the first volatile memory for a first pass, wherein the buffer manager sends the data read from the first volatile memory through an encoder channel to generate encoded data for programming into the flash memory for the first pass;
communicating with the buffer manager to store the encoded data in a second volatile memory to be used for programming into the flash memory for subsequent passes after the first pass, wherein the programming of the encoded data into the flash memory for the first pass is performed by bypassing the second volatile memory; and
communicating with the buffer manager to read the encoded data from the second volatile memory to program the flash memory for the subsequent passes, wherein the buffer manager sends the encoded data to the flash memory through a bypass channel.
12. The method of claim 11 , wherein the buffer manager stores the encoded data in the second volatile memory through a write back channel.
13. The method of claim 11 , wherein once the encoded data is stored in the second volatile memory, the first volatile memory is released for next data transfer with the host system.
14. The method of claim 11 , wherein the M is 3 and the plurality of M-level cells include triple level cells (TLCs).
15. The method of claim 11 , wherein the first volatile memory is a static random access memory (SRAM) and the second volatile memory is a dynamic random access memory (DRAM).
16. The method of claim 11 , wherein the first volatile memory is on a same chip as the processor, and the second volatile memory is not on the same chip.
17. The method of claim 11 , wherein the method is performed by a flash memory controller for a flash memory device.
18. A non-transitory computer readable medium having stored thereon instructions that, when executed by a processor, perform a method, comprising:
receiving a request from a host system with data to be written into a flash memory, wherein the data is stored in a first volatile memory, wherein the flash memory includes a flash memory block comprising a plurality of pages, each page comprising a plurality of M-level cells, wherein each page of data is programmed into the flash memory in multiple passes by writing a same page of data to a respective page of the plurality of M-level cells of the flash memory for each of the multiple passes;
communicating with a buffer manager, communicatively coupled to the processor, to read the data stored in the first volatile memory, wherein the buffer manager sends the data read from the first volatile memory through an encoder channel to generate encoded data for programming into the flash memory for the first pass, wherein the programming of the encoded data into the flash memory for the first pass is performed by bypassing the second volatile memory;
communicating with the buffer manager to store the encoded data in a second volatile memory to be used for programming into the flash memory for subsequent passes after the first pass; and
communicating with the buffer manager to read the encoded data from the second volatile memory to program the flash memory for the subsequent passes, wherein the buffer manager sends the encoded data to the flash memory through a bypass channel.
19. The non-transitory computer readable medium of claim 18 , wherein the processor is part of a flash memory controller for a flash memory device.
20. The non-transitory computer readable medium of claim 19 , wherein the M is 3 and the plurality of M-level cells include triple level cells (TLCs).