IP Library Patent Application 15415462
Patent Application
App. No. 15/415,462

Semiconductor Device and Method of Forming Inverted Pyramid Cavity Semiconductor Package

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Quick Facts
Patent No.
US None
App. No.
15/415,462
Abstract

A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.

Claims (44)

1 . A semiconductor device, comprising:

a first substrate including a first cavity formed through the first substrate;

a conductive layer formed over a surface of the first substrate with the conductive layer exposed in the first cavity;

a first semiconductor die disposed in the first cavity and on the conductive layer;

a second substrate including a second cavity disposed over the first substrate with the second cavity larger than the first cavity; and

a second semiconductor die disposed in the second cavity.

2 . The semiconductor device of claim 1 , wherein a portion of the first substrate is exposed within the second cavity.

3 . The semiconductor device of claim 2 , wherein the second semiconductor die is disposed over the portion of the first substrate exposed within the second cavity.

4 . The semiconductor device of claim 1 , further including a passive device disposed over the second substrate and second semiconductor die.

5 . The semiconductor device of claim 1 , further including an encapsulant deposited in the first cavity around the first semiconductor die and in the second cavity around the second semiconductor die.

6 . The semiconductor device of claim 1 , further including a heat spreader disposed over the second substrate and second semiconductor die.

7 . A semiconductor device, comprising:

a first substrate including a first cavity;

a conductive layer formed over the first substrate and first cavity;

a first semiconductor die disposed in the first cavity and electrically coupled to the conductive layer;

a second substrate including a second cavity disposed over the first substrate; and

a second semiconductor die disposed in the second cavity on the first substrate.

8 . The semiconductor device of claim 7 , further including a third semiconductor die disposed over the second substrate.

9 . The semiconductor device of claim 8 , further including a heat spreader disposed over the third semiconductor die.

10 . The semiconductor device of claim 7 , further including:

a plurality of first conductive bumps extending from the first semiconductor die to the conductive layer; and

a plurality of second conductive bumps extending from the second semiconductor die to the first substrate.

11 . The semiconductor device of claim 7 , further including a first conductive via formed through the first semiconductor die.

12 . The semiconductor device of claim 11 , further including a second conductive via formed through the second semiconductor die over the first conductive via.

13 . The semiconductor device of claim 7 , wherein the second cavity extends to a surface of the first substrate.

14 . A semiconductor device, comprising:

a first substrate including a first cavity;

a conductive layer formed over the first substrate and first cavity;

a first semiconductor die disposed in the first cavity; and

a second substrate disposed over the first substrate including a second cavity of the second substrate aligned with the first cavity of the first substrate.

15 . The semiconductor device of claim 14 , wherein the second cavity is larger than the first cavity.

16 . The semiconductor device of claim 14 , further including a second semiconductor die disposed on the second substrate over the second cavity.

17 . The semiconductor device of claim 16 , further including a heat spreader disposed over the second semiconductor die.

18 . The semiconductor device of claim 17 , further including an encapsulant deposited over the first semiconductor die and second semiconductor die with the heat spreader exposed from the encapsulant.

19 . The semiconductor device of claim 14 , further including a discrete passive device disposed on the second substrate over the second cavity.

20 . A semiconductor device, comprising:

a first substrate including a first cavity;

a first semiconductor die disposed in the first cavity; and

a second substrate disposed over the first substrate including a second cavity of the second substrate aligned with the first cavity of the first substrate.

21 . The semiconductor device of claim 20 , further including a conductive layer formed over the first substrate and first cavity with the first semiconductor die disposed on the conductive layer.

22 . The semiconductor device of claim 20 , wherein the second cavity is larger than the first cavity.

23 . The semiconductor device of claim 20 , further including a second semiconductor die disposed in the second cavity.

24 . The semiconductor device of claim 23 , wherein the second semiconductor die is disposed on the first substrate.

25 . The semiconductor device of claim 20 , wherein the first cavity is formed completely through the first substrate.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jul 8, 2026
From: JPMORGAN CHASE BANK, N.A.
To: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
Reel/Frame 075211/0699 →
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (042210/0702) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0705 →
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (043070/0051) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0735 →
SECURITY INTEREST Recorded Jul 21, 2017
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 043070/0051 →
SECURITY INTEREST Recorded May 2, 2017
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 042210/0702 →