IP Library Granted Patent US 10,262,606
Granted Patent B2
US 10,262,606 · App. 15/417,703 · Granted Apr 16, 2019

Display device

Inventor: Takehiro Shima (Tokyo, JP)
Assignee: Japan Display Inc.
G09G3/3611G02F1/1362G02F1/13454G09G3/20G09G3/3648G02F2201/56G09G2300/04G09G2300/0426G09G2300/0452G09G2300/0857G09G2310/0278G09G2310/0291G09G2310/08G11C11/41
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Quick Facts
Patent No.
US 10,262,606
App. No.
15/417,703
Granted
Apr 16, 2019
Kind
B2
Abstract

According to one embodiment, a display device includes a pair of substrates including a display area in which pixels are arranged, pixel electrodes and memories provided in the pixels, signal lines supplied with digital signals, switching elements connecting the memories and the signal lines, scanning lines supplied with scanning signals, a first driver unit, and a second driver unit. The first driver unit is provided in a peripheral area around the display area, and supplies the digital signal to the signal line. The second driver unit is provided in the peripheral area, and supplies the scanning signal to the scanning line. In the display device, at least a part of the first driver unit is provided between the display area and the second driver unit.

Claims (89)

1. A display device comprising:

a pair of substrates comprising a display area in which a plurality of pixels are arranged;

an optical element layer provided between the pair of substrates;

pixel electrodes provided in the respective pixels;

memories provided in the respective pixels;

signal lines supplied with digital signals to be stored in the memories;

switching elements connecting the memories and the signal lines;

scanning lines supplied with scanning signals for controlling the switching elements;

a first driver unit which is provided in a peripheral area around the display area and is configured to supply the digital signals to the signal lines; and

a second driver unit which is provided in the peripheral area and is configured to supply the scanning signals to the scanning lines; and

a power line configured to supply power to the memory, wherein

the first driver unit comprises p plurality of first circuit units,

the signal lines are connected to the respective first circuit units,

at least one of the first circuit units is provided between the display area and the second driver unit,

the first circuit units include a first circuit, a second circuit, and a first connective line connecting the first circuit and the second circuit,

in a planar view, the scanning line intersects with the first connective line and extends in a first direction between the first circuit and the second circuit, and

in a planar view, the power line further intersects with the first connective line and extends between the first circuit and the second circuit.

2. The display device of claim 1 , wherein

the first circuit includes a shift register, and

the second circuit includes a first latch circuit configured to store the digital signal supplied to the signal line.

3. The display device of claim 1 , further comprising a data bus supplied with data indicating the digital signals to be stored in the memories of the pixels in series, wherein

in a planar view, the data bus further intersects with the first connective line and extends between the first circuit and the second circuit.

4. The display device of claim 1 , wherein

the scanning lines include a first scanning line and a second scanning line,

the first circuit unit includes a first circuit, a second circuit, a third circuit, a first connective line connecting the first circuit and the second circuit, and a second connective line connecting the second circuit and the third circuit,

in a planar view, the first scanning line intersects with the first connective line and extends in a first direction between the first circuit and the second circuit, and

in a planar view, the second scanning line intersects with the second connective line and extends in the first direction between the second circuit and the third circuit.

5. The display device of claim 4 , wherein

the first circuit includes a shift register,

the second circuit includes a first latch circuit configured to store the digital signal supplied to the signal line, and

the third circuit includes a second latch circuit configured to store the digital signal output from the first latch circuit.

6. The display device of claim 5 , wherein

the third circuit further comprises a buffer circuit, and a third connective line connecting the second latch circuit and the buffer circuit, and

the buffer circuit is configured to supply the digital signal stored in the second latch circuit to the signal line.

7. A display device comprising:

a pair of substrates comprising a display area in which a plurality of pixels are arranged;

an optical element layer provided between the pair of substrates;

pixel electrodes provided in the respective pixels;

memories provided in the respective pixels;

signal lines supplied with digital signals to be stored in the memories;

switching elements connecting the memories and the signal lines;

scanning lines supplied with scanning signals for controlling the switching elements;

a first driver unit which is provided in a peripheral area around the display area and is configured to supply the digital signals to the signal lines;

a second driver unit which is provided in the peripheral area and is configured to supply the scanning signals to the scanning lines;

a first line supplied with a display signal for an image;

a second line supplied with a non-display signal for an image; and

a select control circuit configured to supply the display signal or the non-display signal to the pixel electrode in accordance with the digital signal stored in the memory, wherein

at least a part of the first driver unit is provided between the display area and the second driver unit, and

at least one of the first line and the second line extends between the display area and the first driver unit.

8. The display device of claim 7 , wherein

at least one of the first line and the second line is bent in a stepwise pattern including a first stage and a second stage, and

the number of first circuit units corresponding to the first stage is different from the number of first circuit units corresponding to the second stage.

9. The display device of claim 7 , further comprising dummy pixels which do not display an image, wherein

the first driver unit comprises a plurality of first circuit units, and

the first circuit units are connected to the respective signal lines, and the number of the dummy pixels connected to each signal line differs.

10. The display device of claim 7 , wherein

the display area is circular, and

the first driver unit and the second driver unit have an arc-shape along a marginal portion of the display area.

11. The display device of claim 7 , wherein

the first driver unit comprises a plurality of first circuit units,

the signal lines are connected to the respective first circuit units, and

at least one of the first circuit units is provided between the display area and the second driver unit.

12. The display device of claim 11 , wherein

the first circuit units include a first circuit, a second circuit, and a first connective line connecting the first circuit and the second circuit, and

in a planar view, the scanning line intersects with the first connective line and extends in a first direction between the first circuit and the second circuit.

13. The display device of claim 12 , wherein

the first circuit includes a shift register, and

the second circuit includes a first latch circuit configured to store the digital signal supplied to the signal line.

14. The display device of claim 13 , further comprising a data bus supplied with data indicating the digital signals to be stored in the memories of the pixels in series, wherein

in a planar view, the data bus further intersects with the first connective line and extends between the first circuit and the second circuit.

15. The display device of claim 14 , further comprising a power line configured to supply power to the memory, wherein

in a planar view, the power line further intersects with the first connective line and extends between the first circuit and the second circuit.

16. A display device comprising:

a pair of substrates comprising a display area in which a plurality of pixels are arranged;

an optical element layer provided between the pair of substrates;

pixel electrodes provided in the respective pixels;

memories provided in the respective pixels;

signal lines supplied with digital signals to be stored in the memories;

switching elements connecting the memories and the signal lines;

scanning lines supplied with scanning signals for controlling the switching elements;

a first driver unit which is provided in a peripheral area around the display area and is configured to supply the digital signals to the signal lines; and

a second driver unit which is provided in the peripheral area and is configured to supply the scanning signals to the scanning lines, wherein

at least a part of the first driver unit is provided between the display area and the second driver unit,

the first driver unit comprises a plurality of first circuit units,

the second driver unit comprises a plurality of second circuit units,

the peripheral area comprises a first area in which at least one of the first circuit units and at least one of the second circuit units are formed, and a second area in which at least one of the second circuit units are formed and the first circuit units are not formed,

a distance between the second circuit unit and the display area in the first area is a first distance,

a distance between the second circuit unit and the display area in the second area is a second distance, and

the second distance is less than the first distance.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2017
From: SHIMA, TAKEHIRO
To: JAPAN DISPLAY INC.
Reel/Frame 041105/0065 →
Priority Claims (1)
JP 2016-016115 · Jan 29, 2016 · national
Continuity (1)
Related Publication 20170221435A1 · Aug 3, 2017