IP Library Granted Patent US 9,826,179
Granted Patent B2
US 9,826,179 · App. 15/418,926 · Granted Nov 21, 2017

Image reading apparatus and semiconductor device

Inventor: Shunichi Shima (Nagano, JP)
Assignee: Seiko Epson Corporation
H04N5/3575H04N1/0308H04N1/193H04N5/3452H04N5/355H04N5/37457H01L27/14612H01L27/14643H04N2201/0081H04N2201/0082
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Quick Facts
Patent No.
US 9,826,179
App. No.
15/418,926
Granted
Nov 21, 2017
Kind
B2
Abstract

An image reading apparatus includes an image reading chip configured to read an image. The image reading chip includes a first pixel unit which generates a first pixel signal, a second pixel unit which generates a second pixel signal, a first amplification unit which amplifies the first pixel signal, and outputs a first amplification signal, a second amplification unit which amplifies the second pixel signal, and outputs a second amplification signal, and a third amplification unit that amplifies each of the first amplification signal and the second amplification signal, and outputs an amplified signal. The image reading chip has a shape which includes a first side and a second side shorter than the first side. The third amplification unit is disposed between the first amplification unit and the second amplification unit in a direction along the first side.

Claims (45)

1. An image reading apparatus comprising:

an image reading chip that reads an image,

wherein

the image reading chip includes

a first pixel unit that includes a first light receiving element configured to receive light from the image and perform photoelectric conversion, and generates a first pixel signal,

a second pixel unit that includes a second light receiving element configured to receive light from the image and perform photoelectric conversion, and generates a second pixel signal,

a first amplification unit that is electrically connected to the first pixel unit, amplifies the first pixel signal, and outputs a first amplification signal,

a second amplification unit that is electrically connected to the second pixel unit, amplifies the second pixel signal, and outputs a second amplification signal, and

a third amplification unit that amplifies each of the first amplification signal and the second amplification signal, and outputs an amplified signal,

the image reading chip has a shape which includes a first side and a second side shorter than the first side, and

the third amplification unit is disposed between the first amplification unit and the second amplification unit in a direction along the first side.

2. The image reading apparatus according to claim 1 , wherein

the third amplification unit is provided at a position of overlapping at least one of the first pixel unit and the second pixel unit in a direction along the second side.

3. The image reading apparatus according to claim 1 , wherein

the sum of a length of the first pixel unit and a length of the second pixel unit in the direction along the first side is larger than the sum of a length of the first amplification unit and a length of the second amplification unit.

4. The image reading apparatus according to claim 1 , wherein

the first amplification unit, the second amplification unit, and the third amplification unit are electrically connected to a common ground wiring.

5. The image reading apparatus according to claim 1 , wherein

the first amplification unit and the third amplification unit are disposed so as to be adjacent to each other, and

the second amplification unit and the third amplification unit are disposed so as to be adjacent to each other.

6. The image reading apparatus according to claim 1 , wherein

the first amplification unit includes a first transistor

the second amplification unit includes a second transistor,

the third amplification unit includes a third transistor, and

the first transistor, the second transistor, and the third transistor are provided at positions which overlap each other in the direction along the first side.

7. The image reading apparatus according to claim 6 , wherein

a threshold voltage of the first transistor, a threshold voltage of the second transistor, and a threshold voltage of the third transistor are substantially equal to each other.

8. The image reading apparatus according to claim 6 , wherein

an overdrive voltage of the first transistor, an overdrive voltage of the second transistor, and an overdrive voltage of the third transistor are substantially equal to each other.

9. The image reading apparatus according to claim 6 , wherein

the first amplification unit includes a first source-grounded type amplifier in which a plurality of transistors including the first transistor is cascode-connected to each other,

the second amplification unit includes a second source-grounded type amplifier in which a plurality of transistors including the second transistor is cascode-connected to each other, and

the third amplification unit includes a third source-grounded type amplifier in which a plurality of transistors including the third transistor is cascode-connected to each other.

10. The image reading apparatus according to claim 1 , wherein

the third amplification unit has characteristics in which an output voltage is lowered as illumination is increased.

11. The image reading apparatus according to claim 1 , further comprising:

a fourth amplification unit that performs non-inverting amplification on an output signal from the third amplification unit, so as to generate an output signal of the image reading chip.

12. A semiconductor device which has a shape including a first side and a second side shorter than the first side, the device comprising:

a first pixel unit that includes a first light receiving element configured to receive light and perform photoelectric conversion, and generates a first pixel signal;

a second pixel unit that includes a second light receiving element configured to receive light and perform photoelectric conversion, and generates a second pixel signal;

a first amplification unit that is electrically connected to the first pixel unit, amplifies the first pixel signal, and outputs a first amplification signal;

a second amplification unit that is electrically connected to the second pixel unit, amplifies the second pixel signal, and outputs a second amplification signal; and

a third amplification unit that amplifies each of the first amplification signal and the second amplification signal, and outputs an amplified signal,

wherein

the third amplification unit is disposed between the first amplification unit and the second amplification unit in a direction along the first side.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 1, 2024
From: SEIKO EPSON CORPORATION
To: CRYSTAL LEAP ZRT
Reel/Frame 066162/0434 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2017
From: SHIMA, SHUNICHI
To: SEIKO EPSON CORPORATION
Reel/Frame 041119/0350 →
Priority Claims (1)
JP 2016-035534 · Feb 26, 2016 · national
Continuity (1)
Related Publication 20170251152A1 · Aug 31, 2017