Systems and methods for solving computational problems
View Patent ↗Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.
1. A method of solving a problem via a first digital processor and an analog processor, the analog processor comprising:
a first set of qubits, communicatively coupled to a first annealing signal line;
a second set of qubits, communicatively coupled to a second annealing signal line;
a first set of couplers, communicatively coupling at least two of the qubits in the first set of qubits;
a second set of couplers, communicatively coupling at least two of the qubits in the second set of qubits; and
a first set of inter-set couplers, communicatively coupling at least one qubit in the first set of qubits and at least one qubit in the second set of qubits, the method comprising:
generating a logic circuit representation of the problem using the first digital processor, wherein the logic circuit representation comprises a first layer and a second layer, and the first and the second layer are sequential operations and the second layer uses at least part of a first layer's output as an input;
encoding the logic circuit representation as a discrete optimization problem;
mapping the discrete optimization problem to the analog processor, wherein the first layer of the logic circuit representation is mapped to the first set of qubits and the second layer of the logic circuit representation is mapped to the second set of qubits;
applying a first annealing waveform to the first annealing signal line to evolve a respective state of each one of the qubits in the first set of qubits; and
applying a second annealing waveform to the second annealing signal line to evolve a respective state of each one of the qubits in the second set of qubits, after the evolution of the first annealing waveform completes.
2. The method of claim 1 wherein the analog processor is a quantum processor and mapping the discrete optimization problem to the analog processor comprises mapping the discrete optimization problem to the quantum processor.
3. The method of claim 1 wherein at least one of the first or the second annealing waveform evolve non-linearly.
4. The method of claim 1 wherein the analog processor further comprises:
a third set of qubits, communicatively coupled to a third annealing signal line;
a third set of couplers, communicatively coupling at least two of the qubits in the third set of qubits; and
a second set of inter-set couplers, communicatively coupling at least one qubit in the second set of qubits and at least one qubit in the third set of qubits; and wherein the logic circuit representation of the problem further comprises a third layer and the third layer executes sequentially after the second layer and the third layer uses at least part of a second layer's output as an input; the method further comprising:
mapping the third layer of the logic circuit representation to the third layer of qubits; and
applying a third annealing waveform to the third annealing signal line after the evolution of the second annealing waveform completes.
5. A system for solving a problem, the system comprising:
an analog processor, the analog processor comprising:
a first set of qubits, communicatively coupled to a first annealing signal line;
a second set of qubits, communicatively coupled to a second annealing signal line;
a first set of couplers, communicatively coupling at least two of the qubits in the first set of qubits;
a second set of couplers, communicatively coupling at least two of the qubits in the second set of qubits; and
a first set of inter-set couplers, communicatively coupling at least one qubit in the first set of qubits and at least one qubit in the second set of qubits; and
a first digital processor, wherein the first digital processor:
generates a logic circuit representation of the problem, the logical representation having a first layer and a second layer, and the first and the second layer are sequential operations and the second layer uses at least part of a first layer's output as an input;
encodes the logic circuit representation as a discrete optimization problem;
maps the discrete optimization problem to the analog processor, wherein the first layer of the logic circuit representation is mapped to the first set of qubits and the second layer of the logic circuit representation is mapped to the second set of qubits;
applies a first annealing waveform to the first annealing signal line to evolve a respective state of each one of the qubits in the first set of qubits; and
applies a second annealing waveform to the second annealing signal line to evolve a respective state of each one of the qubits in the second set of qubits, after the evolution of first annealing waveform completes.
6. The system of claim 5 wherein the analog processor is a quantum processor.
7. The system of claim 5 wherein at least one of the first or the second annealing waveform evolve non-linearly.
8. The system of claim 5 wherein the analog processor further comprises:
a third set of qubits communicatively coupled to a third annealing signal line;
a third set of couplers, communicatively coupling at least two of the qubits in the third set of qubits; and
a second set of inter-set couplers, communicatively coupling at least one qubit in the second set of qubits and at least one qubit in the third set of qubits; and
wherein the logic circuit representation of the problem further comprises a third layer, and the third layer executes sequentially after the second layer and the third layer uses at least part of a second layer's output as an input;
wherein the first digital processor:
maps the third layer of the logic circuit representation to the third layer of qubits; and
applies a third annealing waveform to the third annealing signal line after the evolution of the second annealing waveform completes.