Display driver and display panel module
View Patent ↗Provided is a display driver which can be used in common in any of COF mounting and COG mounting. In the display driver, a position (or write/output position) of display data output by an output circuit can be changed along a direction of an array of external output terminals S 1 to S 540 according to mode data, whereby an array of external output terminals to use for output can be selected from more than one kind of arrays different in layout pitch. Therefore, the display driver can be used in display panels with signals lines having different pitches serving to receive drive signals from the display driver and in addition, used in common in any of COF mounting and COG mounting which are different from each other in the pitch of mounting wiring lines.
1. A display driver formed as a semiconductor integrated circuit of an elongated shape, the display driver comprising:
a plurality of external output terminals regularly disposed along a lengthwise direction of the display driver;
an output circuit operable to produce display drive signals to supply to a display panel using required external output terminals;
an output mode register on which output mode data are set overwritably; and
a control circuit operable to perform control for selecting an array of the external output terminals to be used by the output circuit for outputting the display drive signals from more than one kind of arrays different in layout pitch according to the output mode data set on the output mode register.
2. The display driver according to claim 1 , wherein the output circuit comprises:
a line latch circuit having data registers arranged in parallel for holding pixel data; and
a drive circuit operable to produce, in units of pixel data, display drive signals from pixel data output by the line latch circuit and provide the display drive signals to the external output terminals, and
wherein the control circuit is configured to perform write address control for sequentially writing pixel data into the line latch circuit according to the output mode data, and output control for outputting, in parallel, outputs of the data registers with pixel data written therein to the drive circuit.
3. The display driver according to claim 2 , wherein the data registers each hold pixel data of more than one pixel as one unit, and
the drive circuit is configured to output, in a time-sharing manner, drive signals corresponding to pixel data of more than one pixel output by the data registers in the units of pixel data.
4. The display driver according to claim 2 , wherein the control circuit has program sequence control logics which decrypt output mode data set on the output mode register and produce control signals for the write address control and output control.
5. The display driver according to claim 1 , wherein the more than one kind of arrays which can be selected by the control circuit comprise an array of the external output terminals in which the condition of a pitch allocated for spacing between adjacent terminals of the external output terminals used for outputting drive signals is changed, and the external output terminals used for outputting drive signals are arrayed from both ends toward the center thereof along a lengthwise direction of the array.
6. The display driver according to claim 5 , wherein the more than one kind of arrays which can be selected by the control circuit comprise an array of the external output terminals in which the number of the external output terminals used for outputting drive signals is changed, and the external output terminals used for outputting drive signals are arrayed from both ends toward the center thereof along a lengthwise direction of the array.
7. A display driver for outputting display drive signals to display elements of a display panel, which is formed as a semiconductor integrated circuit of an elongated shape, the display driver comprising:
a plurality of external output terminals regularly disposed along a lengthwise direction of the display driver;
an output circuit operable to produce display drive signals to supply to a display panel from required external output terminals;
a host interface circuit;
a register circuit to input control data from the host interface circuit; and
a control circuit operable to produce control signals based on the control data set on the register circuit,
wherein the register circuit has an output mode register on which output mode data are set overwritably,
the control circuit is configured to perform control for selecting an array of the external output terminals to be used by the output circuit for outputting the display drive signals from more than one kind of arrays different in layout pitch according to output mode data set on the output mode register, and
the more than one kind of arrays which can be selected by the control circuit comprise an array of the external output terminals in which the condition of a pitch allocated for spacing between adjacent terminals of the external output terminals used for outputting drive signals is changed.
8. The display driver according to claim 7 , wherein the more than one kind of arrays which can be selected by the control circuit further comprise an array of the external output terminals in which the number of the external output terminals used for outputting drive signals is changed.
9. The display driver according to claim 7 , wherein the more than one kind of arrays which can be selected by the control circuit comprise an array in which the external output terminals used for outputting drive signals are arrayed from both ends toward the center thereof along a lengthwise direction of the array.
10. The display driver according to claim 7 , wherein the output circuit comprises: a line latch circuit having data registers arranged in parallel for holding pixel data; and a drive circuit operable to produce, in units of pixel data, display drive signals from pixel data output by the line latch circuit and then provide the display drive signals to the external output terminals, and
the control circuit is configured to perform write address control for sequentially writing pixel data into the line latch circuit according to the output mode data and output control for outputting, in parallel, outputs of the data registers with pixel data written therein to the drive circuit.
11. The display driver according to claim 10 , wherein the data registers each hold pixel data of more than one pixel as one unit, and
the drive circuit is configured to output, in a time-sharing manner, drive signals corresponding to pixel data of more than one pixel output by the data registers in the units of pixel data.
12. A display panel module comprising:
a display panel having display elements arrayed in a matrix form; and
a display driver formed as a semiconductor integrated circuit of an elongated shape, and supplying display drive signals to the display panel,
wherein the display driver comprises:
a plurality of external output terminals regularly disposed along a lengthwise direction of the display driver;
an output circuit operable to produce display drive signals to supply to the display panel using required external output terminals;
an output mode register on which output mode data are set overwritably; and
a control circuit operable to perform control for selecting an array of the external output terminals to be used by the output circuit for outputting the display drive signals from more than one kind of arrays different in layout pitch according to the output mode data set on the output mode register, and
wherein the more than one kind of arrays which can be selected by the control circuit comprise an array of the external output terminals in which the condition of a pitch allocated for spacing between adjacent terminals of the external output terminals used for outputting drive signals is changed.
13. The display panel module according to claim 12 , wherein the more than one kind of arrays which can be selected by the control circuit further comprise an array of the external output terminals in which the number of the external output terminals used for outputting drive signals is changed.
14. The display panel module according to claim 12 , wherein the more than one kind of arrays which can be selected by the control circuit comprise an array in which the external output terminals used for outputting drive signals are arrayed from both ends toward the center thereof along a lengthwise direction of the array.
15. The display panel module according to claim 12 , wherein the display driver is mounted on a glass substrate of the display panel according to a chip-on-glass (COG) form, and
the external output terminals are directly bonded to a wiring pattern on the glass substrate of the display panel.
16. The display panel module according to claim 12 , wherein the display driver is mounted on a flexible wiring board connected to the display panel according to a chip-on-film (COF) form, and
the external output terminals are directly bonded to wiring lines of the flexible wiring board, and connected to a wiring pattern on a glass substrate of the display panel.
17. The display panel module according to claim 12 , wherein the output circuit comprises:
a line latch circuit having data registers arranged in parallel for holding pixel data; and
a drive circuit operable to produce, in units of pixel data, display drive signals from pixel data output by the line latch circuit and provide the display drive signals to the external output terminals, and
wherein the control circuit is configured to perform write address control for sequentially writing pixel data into the line latch circuit according to the output mode data and output control for outputting, in parallel, outputs of the data registers with pixel data written therein to the drive circuit.
18. The display panel module according to claim 17 , wherein the data registers each hold pixel data of more than one pixel as one unit, and
the drive circuit in configured to output, in a time-sharing manner, drive signals corresponding to pixel data of more than one pixel output by the data registers in the units of pixel data,
the display panel comprises select circuits for supplying drive signals, sequentially output by the drive circuit in a time sharing manner, to signal lines of corresponding display elements in units of pixel data of corresponding pixels, and
the control circuit is configured to perform selective control for causing the select circuits to select the signal lines of the display elements corresponding to drive signals output in the time sharing manner in synchronization with the drive signals output by the drive circuit in the time sharing manner.