IP Library Granted Patent US 10,223,485
Granted Patent B2
US 10,223,485 · App. 15/420,448 · Granted Mar 5, 2019

Reliability verification based on combining voltage propagation with simulation

Inventors: Sridhar Srinivasan (Tualatin, OR); Mark E. Hofmann (Portland, OR)
Assignee: Mentor Graphics Corporation
G06F17/5036G06F17/504
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Quick Facts
Patent No.
US 10,223,485
App. No.
15/420,448
Granted
Mar 5, 2019
Kind
B2
Abstract

Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.

Claims (37)

1. One or more computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

determining voltage values on nets of a circuit design based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits, wherein:

the one or more subcircuits are identified based on circuit topology recognition,

the propagating is based on performing global iterations of the entire circuit design in combination with performing local iterations of the one or more subcircuits,

at least one of the global iterations comprises performing local iterations for one of the one or more subcircuits of the circuit design while voltage values on nets of the subcircuit are unstable with respect to the at least one of the global iterations, and suspending performing the local iterations for the one of the one or more subcircuits of the circuit design when the voltage values on the nets of the subcircuit become stable with respect to the at least one of the global iterations;

analyzing the determined voltage values to detect problems in the circuit design; and

reporting the detected problems in the circuit design, wherein the reported detected problems are thereafter used in a design automation process to correct the circuit design, and the corrected circuit design is usable for manufacturing a device using a photolithographic process.

2. The one or more computer-readable media recited in claim 1 , wherein the propagating voltage values is performed across components of the circuit design except components of the one or more subcircuits.

3. The one or more computer-readable media recited in claim 1 , wherein the circuit topology recognition comprises design pattern matching, component tracing or both.

4. The one or more computer-readable media recited in claim 1 , wherein the one or more subcircuits are identified based further on voltage propagation.

5. The one or more computer-readable media recited in claim 1 , wherein the simulating employs a SPICE (Simulation Program with Integrated Circuit Emphasis) simulation tool.

6. The one or more computer-readable media recited in claim 1 , wherein the problems in the circuit design comprise electrical overstress, electrostatic discharge, or both.

7. The one or more computer-readable media recited in claim 1 , wherein the reporting comprises storing and/or displaying information of the detected problems.

8. A method, executed by at least one processor of a computer, comprising:

determining voltage values on nets of a circuit design based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits, wherein:

the one or more subcircuits are identified based on circuit topology recognition,

the propagating is based on performing global iterations of the entire circuit design in combination with performing local iterations of the one or more subcircuits, and

at least one of the global iterations comprises performing local iterations for one of the one or more subcircuits of the circuit design while voltage values on nets of the subcircuit are unstable with respect to the at least one of the global iterations, and suspending performing the local iterations for the one of the one or more subcircuits of the circuit design when the voltage values on the nets of the subcircuit become stable with respect to the at least one of the global iterations;

analyzing the determined voltage values to detect problems in the circuit design; and

reporting the detected problems in the circuit design, wherein the reported detected problems are thereafter used in a design automation process to correct the circuit design, and the corrected circuit design is usable for manufacturing a device using a photolithographic process.

9. The method recited in claim 8 , wherein the propagating voltage values is performed across components of the circuit design except components of the one or more subcircuits.

10. The method recited in claim 8 , wherein the circuit topology recognition comprises design pattern matching, component tracing or both.

11. The method recited in claim 8 , wherein the one or more subcircuits are identified based further on voltage propagation.

12. The method recited in claim 8 , wherein the simulating employs a SPICE (Simulation Program with Integrated Circuit Emphasis) simulation tool.

13. The method recited in claim 8 , wherein the problems in the circuit design comprise electrical overstress, electrostatic discharge, or both.

14. The method recited in claim 8 , wherein the reporting comprises storing and/or displaying information of the detected problems.

15. A system comprising:

one or more processors, the one or more processors programmed to perform a method, the method comprising:

determining voltage values on nets of a circuit design based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits, wherein:

the one or more subcircuits are identified based on circuit topology recognition,

the propagating is based on performing global iterations of the entire circuit design in combination with performing local iterations of the one or more subcircuits, and

at least one of the global iterations comprises performing local iterations for one of the one or more subcircuits of the circuit design while voltage values on nets of the subcircuit are unstable with respect to the at least one of the global iterations, and suspending performing the local iterations for the one of the one or more subcircuits of the circuit design when the voltage values on the nets of the subcircuit become stable with respect to the at least one of the global iterations;

analyzing the determined voltage values to detect problems in the circuit design; and

reporting the detected problems in the circuit design, wherein the reported detected problems are thereafter used in a design automation process to correct the circuit design, and the corrected circuit design is usable for manufacturing a device using a photolithographic process.

16. The system recited in claim 15 , wherein the propagating voltage values is performed across components of the circuit design except components of the one or more subcircuits.

17. The system recited in claim 15 , wherein the circuit topology recognition comprises design pattern matching, component tracing or both.

18. The system recited in claim 15 , wherein the one or more subcircuits are identified based further on voltage propagation.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jun 28, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056688/0930 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2017
From: SRINIVASAN, SRIDHAR; HOFMANN, MARK E.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 041185/0981 →
Continuity (1)
Related Publication 20180218100A1 · Aug 2, 2018