IP Library Granted Patent US 10,296,378
Granted Patent B2
US 10,296,378 · App. 15/420,659 · Granted May 21, 2019

Efficient processor load balancing using predication

Inventors: Vinod Tipparaju (Austin, TX); Lee Howes (Austin, TX); Thomas Scogland (Blacksburg, VA)
Assignee: ADVANCED MICRO DEVICES, INC.
G06F9/4881G06F9/505G06F9/5083
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Quick Facts
Patent No.
US 10,296,378
App. No.
15/420,659
Granted
May 21, 2019
Kind
B2
Abstract

A system and methods embodying some aspects of the present embodiments for efficient load balancing using predication flags are provided. The load balancing system includes a first processing unit, a second processing unit, and a shared queue. The first processing unit is in communication with a first queue. The second processing unit is in communication with a second queue. The first and second queues are each configured to hold a packet. The shared queue is configured to maintain a work assignment, wherein the work assignment is to be processed by either the first or second processing unit.

Claims (13)

1. A method comprising:

reading a work assignment pointer from a packet, wherein the work assignment pointer points to a work assignment on a shared queue;

retrieving a work element, and a bit that indicates when the work assignment has been assigned to a processing unit, from the work assignment;

setting the bit in the work assignment; and

executing the work element associated with the work assignment when the retrieved bit is clear,

wherein the retrieving and the setting occur within a single clock cycle.

2. The method of claim 1 , wherein the retrieving and the setting comprise executing an atomic instruction.

3. The method of claim 1 , wherein the retrieving and the setting comprise executing a single instruction.

4. The method of claim 1 , wherein the retrieving the bit comprises storing the bit in memory.

5. The method of claim 1 , wherein the work element comprises the set of instructions to be executed.

6. The method of claim 1 , wherein the work element comprises a pointer to the set of instructions to be executed.

7. The method of claim 1 , further comprising:

storing the packet in a queue, wherein the packet is stored based on characteristics of a processing unit associated with the queue and characteristics of the work element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2019
From: TIPPARAJU, VINOD; HOWES, LEE; SCOGLAND, THOMAS
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 048806/0960 →
Continuity (2)
Division 13897141 · May 17, 2013
Related Publication 20170139748A1 · May 18, 2017