Dynamic triggering and sampling engine (DTSE) for low-latency and cost effective control systems
A Dynamic Triggering and Sample Engine (DTSE) that detects a first trigger received on a trigger input terminal that triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit. The DTSE then determines a first sequence configuration stored in a sequence configuration table that is associated with the first trigger, causes a first analog-to-digital conversion to be performed using the first sequence configuration; causes a first analog-to-digital conversion result value to be stored in a sequence result table; and outputs an interrupt to a processor indicating that the first analog-to-digital conversion result value is available in the sequence result table. The interrupt is output from the DTSE before all remaining analog-to-digital conversions in the series are completed. In response to receiving the interrupt, the processor reads the analog-to-digital result value from the sequence result table via a bus.
1. A Dynamic Triggering and Sample Engine (DTSE), comprising:
a hardware trigger input;
a bus terminal;
a memory that stores a trigger mapping table, a sequence configuration table, and a sequence result table; and
a state machine, wherein the state machine is configured to:
detect a first trigger received on the hardware trigger input, wherein the first trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit;
determine a first sequence configuration stored in the sequence configuration table that is associated with the first trigger;
cause one of the first analog-to-digital conversions to be performed using the first sequence configuration;
cause a first analog-to-digital conversion result value to be stored in the sequence result table; and
output an interrupt indicating that the first analog-to-digital conversion has been completed by the analog-to-digital circuit, wherein the interrupt is output before at least one of the remaining analog-to-digital conversions in the series is completed, wherein the series of analog-to-digital conversions includes critical samples and non-critical samples, and wherein at least one of the critical samples is completed before at least one of the non-critical samples.
2. The DTSE of claim 1 , wherein the interrupt is output after at least one of the critical samples of the series of analog-to-digital conversions are completed.
3. The DTSE of claim 1 , wherein the interrupt is output after at least one of the non-critical samples of the series of analog-to-digital conversions are completed.
4. A Dynamic Triggering and Sample Engine (DTSE), comprising:
a hardware trigger input;
a bus terminal;
a memory that stores a trigger mapping table, a sequence configuration table, and a sequence result table; and
a state machine, wherein the state machine is configured to:
detect a first trigger received on the hardware trigger input, wherein the first trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit;
determine a first sequence configuration stored in the sequence configuration table that is associated with the first trigger;
cause one of the first analog-to-digital conversions to be performed using the first sequence configuration;
cause a first analog-to-digital conversion result value to be stored in the sequence result table; and
output an interrupt indicating that the first analog-to-digital conversion has been completed by the analog-to-digital circuit, wherein the interrupt is output before at least one of the remaining analog-to-digital conversions in the series is completed, wherein the series of analog-to-digital conversions includes critical samples and non-critical samples, wherein at least one of the critical samples is completed before at least one of the non-critical samples, and wherein the trigger mapping table is programmed by another device via the bus terminal.
5. A Dynamic Triggering and Sample Engine (DTSE), comprising:
a hardware trigger input;
a bus terminal;
a memory that stores a trigger mapping table, a sequence configuration table, and a sequence result table; and
a state machine, wherein the state machine is configured to:
detect a first trigger received on the hardware trigger input, wherein the first trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit;
determine a first sequence configuration stored in the sequence configuration table that is associated with the first trigger;
cause one of the first analog-to-digital conversions to be performed using the first sequence configuration;
cause a first analog-to-digital conversion result value to be stored in the sequence result table; and
output an interrupt indicating that the first analog-to-digital conversion has been completed by the analog-to-digital circuit, wherein the interrupt is output before at least one of the remaining analog-to-digital conversions in the series is completed, wherein the series of analog-to-digital conversions includes critical samples and non-critical samples, wherein at least one of the critical samples is completed before at least one of the non-critical samples, and wherein the DTSE and the analog-to-digital converter circuit are both fabricated on a single integrated circuit.
6. The DTSE of claim 1 , wherein the DTSE and a processor circuit are both fabricated on a single integrated circuit, and wherein the interrupt is communicated from the DTSE to the processor circuit.
7. The DTSE of claim 1 , wherein each sequence configuration stored in memory is associated with a unique entry in the sequence result table.
8. The DTSE of claim 1 , wherein the state machine is implemented using a microcontroller.
9. The DTSE of claim 1 , wherein the state machine is implemented using combinatory logic.
10. The DTSE of claim 1 , wherein the bus is an Advanced Microcontroller Bus Architecture (AMBA) bus.
11. The DTSE of claim 1 , wherein the Dynamic Triggering and Sample Engine (DTSE) includes a plurality of hardware trigger inputs.
12. A Dynamic Triggering and Sample Engine (DTSE), comprising:
a hardware trigger input;
a bus terminal;
a memory that stores a trigger mapping table, a sequence configuration table, and a sequence result table; and
a state machine, wherein the state machine is configured to:
detect a first trigger received on the hardware trigger input, wherein the first trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit;
determine a first sequence configuration stored in the sequence configuration table that is associated with the first trigger;
cause one of the first analog-to-digital conversions to be performed using the first sequence configuration;
cause a first analog-to-digital conversion result value to be stored in the sequence result table; and
output an interrupt indicating that the first analog-to-digital conversion has been completed by the analog-to-digital circuit, wherein the interrupt is output before at least one of the remaining analog-to-digital conversions in the series is completed, wherein the DTSE can be configured to detect a rising edge of a Pulse Width Modulate (PWM) signal on the hardware trigger input or a Pulse Width Modulate (PWM) signal on the hardware trigger input.
13. The DTSE of claim 1 , wherein the memory comprises a plurality of storage devices.
14. A method of dynamic triggering, comprising:
(a) detecting a first trigger received on a hardware trigger input, wherein the first trigger triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit;
(b) determining a first sequence configuration stored in a sequence configuration table that is associated with the first trigger;
(c) causing a first analog-to-digital conversion to be performed using the first sequence configuration;
(d) causing a first analog-to-digital conversion result value to be stored in a sequence result table; and
(e) outputting an interrupt indicating that the first analog-to-digital conversion result value is available in the sequence result table, wherein the interrupt is output before at least one of the analog-to-digital conversions in the series are completed, and wherein the outputting of (e) further comprises:
(e1) determining a first portion of the series of analog-to-digital conversions that are critical conversions;
(e2) determining a second portion of the series of analog-to-digital conversions that are non-critical conversions; and
(e3) outputting the interrupt after at least one of the critical conversions are completed and before the non-critical conversions are completed.
15. The method of claim 14 , wherein the first analog-to-digital conversion result value is the result of performing the first analog-to-digital conversion.
16. The method of claim 14 , wherein the steps (a) through (e) are performed by a state machine included in a Dynamic Triggering and Sample Engine (DTSE).
17. The method of claim 14 , further comprising receiving the first sequence configuration from a bus.
18. The method of claim 14 , further comprising communicating the first analog-to-digital conversion result value across a bus.